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![Simon Glass](/assets/img/avatar_default.png)
At present there are a lot of dtoc warnings reported when building chromebook_coral, of the form: WARNING: the driver intel_apl_lpc was not found in the driver list Correct these by using driver names that matches their compatible string. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
206 lines
4.8 KiB
C
206 lines
4.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Primary-to-Sideband Bridge
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*
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* Copyright 2019 Google LLC
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*/
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#define LOG_CATEGORY UCLASS_P2SB
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#include <common.h>
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#include <dm.h>
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#include <dt-structs.h>
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#include <log.h>
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#include <p2sb.h>
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#include <spl.h>
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#include <asm/pci.h>
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#include <linux/bitops.h>
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#define PCH_P2SB_E0 0xe0
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#define HIDE_BIT BIT(0)
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struct p2sb_platdata {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_intel_p2sb dtplat;
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#endif
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ulong mmio_base;
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pci_dev_t bdf;
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};
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/* PCI config space registers */
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#define HPTC_OFFSET 0x60
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#define HPTC_ADDR_ENABLE_BIT BIT(7)
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/* High Performance Event Timer Configuration */
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#define P2SB_HPTC 0x60
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#define P2SB_HPTC_ADDRESS_ENABLE BIT(7)
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/*
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* ADDRESS_SELECT ENCODING_RANGE
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* 0 0xfed0 0000 - 0xfed0 03ff
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* 1 0xfed0 1000 - 0xfed0 13ff
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* 2 0xfed0 2000 - 0xfed0 23ff
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* 3 0xfed0 3000 - 0xfed0 33ff
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*/
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#define P2SB_HPTC_ADDRESS_SELECT_0 (0 << 0)
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#define P2SB_HPTC_ADDRESS_SELECT_1 (1 << 0)
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#define P2SB_HPTC_ADDRESS_SELECT_2 (2 << 0)
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#define P2SB_HPTC_ADDRESS_SELECT_3 (3 << 0)
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/*
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* p2sb_early_init() - Enable decoding for HPET range
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*
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* This is needed by FSP-M which uses the High Precision Event Timer.
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*
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* @dev: P2SB device
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* @return 0 if OK, -ve on error
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*/
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static int p2sb_early_init(struct udevice *dev)
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{
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struct p2sb_platdata *plat = dev_get_platdata(dev);
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pci_dev_t pdev = plat->bdf;
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/*
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* Enable decoding for HPET memory address range.
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* HPTC_OFFSET(0x60) bit 7, when set the P2SB will decode
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* the High Performance Timer memory address range
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* selected by bits 1:0
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*/
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pci_x86_write_config(pdev, HPTC_OFFSET, HPTC_ADDR_ENABLE_BIT,
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PCI_SIZE_8);
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/* Enable PCR Base address in PCH */
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pci_x86_write_config(pdev, PCI_BASE_ADDRESS_0, plat->mmio_base,
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PCI_SIZE_32);
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pci_x86_write_config(pdev, PCI_BASE_ADDRESS_1, 0, PCI_SIZE_32);
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/* Enable P2SB MSE */
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pci_x86_write_config(pdev, PCI_COMMAND, PCI_COMMAND_MASTER |
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PCI_COMMAND_MEMORY, PCI_SIZE_8);
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return 0;
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}
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static int p2sb_spl_init(struct udevice *dev)
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{
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/* Enable decoding for HPET. Needed for FSP global pointer storage */
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dm_pci_write_config(dev, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 |
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P2SB_HPTC_ADDRESS_ENABLE, PCI_SIZE_8);
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return 0;
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}
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int p2sb_ofdata_to_platdata(struct udevice *dev)
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{
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struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev);
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struct p2sb_platdata *plat = dev_get_platdata(dev);
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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int ret;
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u32 base[2];
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ret = dev_read_u32_array(dev, "early-regs", base, ARRAY_SIZE(base));
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if (ret)
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return log_msg_ret("Missing/short early-regs", ret);
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plat->mmio_base = base[0];
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/* TPL sets up the initial BAR */
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if (spl_phase() == PHASE_TPL) {
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plat->bdf = pci_get_devfn(dev);
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if (plat->bdf < 0)
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return log_msg_ret("Cannot get p2sb PCI address",
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plat->bdf);
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}
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upriv->mmio_base = plat->mmio_base;
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#else
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plat->mmio_base = plat->dtplat.early_regs[0];
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plat->bdf = pci_ofplat_get_devfn(plat->dtplat.reg[0]);
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upriv->mmio_base = plat->mmio_base;
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#endif
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return 0;
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}
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static int p2sb_probe(struct udevice *dev)
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{
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if (spl_phase() == PHASE_TPL)
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return p2sb_early_init(dev);
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else if (spl_phase() == PHASE_SPL)
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return p2sb_spl_init(dev);
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return 0;
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}
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static void p2sb_set_hide_bit(struct udevice *dev, bool hide)
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{
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dm_pci_clrset_config8(dev, PCH_P2SB_E0 + 1, HIDE_BIT,
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hide ? HIDE_BIT : 0);
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}
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static int intel_p2sb_set_hide(struct udevice *dev, bool hide)
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{
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u16 vendor;
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if (!CONFIG_IS_ENABLED(PCI))
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return -EPERM;
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p2sb_set_hide_bit(dev, hide);
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dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
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if (hide && vendor != 0xffff)
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return log_msg_ret("hide", -EEXIST);
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else if (!hide && vendor != PCI_VENDOR_ID_INTEL)
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return log_msg_ret("unhide", -ENOMEDIUM);
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return 0;
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}
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static int p2sb_remove(struct udevice *dev)
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{
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int ret;
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ret = intel_p2sb_set_hide(dev, true);
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if (ret)
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return log_msg_ret("hide", ret);
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return 0;
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}
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static int p2sb_child_post_bind(struct udevice *dev)
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{
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
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int ret;
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u32 pid;
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ret = dev_read_u32(dev, "intel,p2sb-port-id", &pid);
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if (ret)
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return ret;
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pplat->pid = pid;
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#endif
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return 0;
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}
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struct p2sb_ops p2sb_ops = {
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.set_hide = intel_p2sb_set_hide,
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};
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static const struct udevice_id p2sb_ids[] = {
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{ .compatible = "intel,p2sb" },
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{ }
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};
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U_BOOT_DRIVER(intel_p2sb) = {
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.name = "intel_p2sb",
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.id = UCLASS_P2SB,
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.of_match = p2sb_ids,
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.probe = p2sb_probe,
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.remove = p2sb_remove,
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.ops = &p2sb_ops,
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.ofdata_to_platdata = p2sb_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct p2sb_platdata),
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.per_child_platdata_auto_alloc_size =
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sizeof(struct p2sb_child_platdata),
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.child_post_bind = p2sb_child_post_bind,
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.flags = DM_FLAG_OS_PREPARE,
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};
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