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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
Quite a few log_info() calls are included in the x86 code which should use log_debug() instead. Convert them to reduce unwanted output. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
169 lines
4.7 KiB
C
169 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Writing IntelGraphicsMem table for ACPI
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*
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* Copyright 2019 Google LLC
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* Modified from coreboot src/soc/intel/gma/opregion.c
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*/
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#include <common.h>
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#include <binman.h>
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#include <bloblist.h>
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#include <dm.h>
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#include <spi_flash.h>
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#include <asm/intel_opregion.h>
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static char vbt_data[8 << 10];
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static int locate_vbt(char **vbtp, int *sizep)
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{
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struct binman_entry vbt;
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struct udevice *dev;
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u32 vbtsig = 0;
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int size;
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int ret;
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ret = binman_entry_find("intel-vbt", &vbt);
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if (ret)
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return log_msg_ret("find VBT", ret);
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ret = uclass_first_device_err(UCLASS_SPI_FLASH, &dev);
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if (ret)
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return log_msg_ret("find flash", ret);
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size = vbt.size;
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if (size > sizeof(vbt_data))
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return log_msg_ret("vbt", -E2BIG);
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ret = spi_flash_read_dm(dev, vbt.image_pos, size, vbt_data);
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if (ret)
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return log_msg_ret("read", ret);
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memcpy(&vbtsig, vbt_data, sizeof(vbtsig));
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if (vbtsig != VBT_SIGNATURE) {
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log_err("Missing/invalid signature in VBT data file!\n");
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return -EINVAL;
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}
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log_debug("Found a VBT of %u bytes\n", size);
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*sizep = size;
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*vbtp = vbt_data;
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return 0;
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}
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/* Write ASLS PCI register and prepare SWSCI register */
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static int intel_gma_opregion_register(struct udevice *dev, ulong opregion)
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{
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int sci_reg;
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if (!device_active(dev))
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return -ENOENT;
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/*
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* Intel BIOS Specification
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* Chapter 5.3.7 "Initialise Hardware State"
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*/
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dm_pci_write_config32(dev, ASLS, opregion);
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/*
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* Atom-based platforms use a combined SMI/SCI register,
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* whereas non-Atom platforms use a separate SCI register
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*/
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if (IS_ENABLED(CONFIG_INTEL_GMA_SWSMISCI))
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sci_reg = SWSMISCI;
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else
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sci_reg = SWSCI;
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/*
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* Intel's Windows driver relies on this:
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* Intel BIOS Specification
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* Chapter 5.4 "ASL Software SCI Handler"
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*/
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dm_pci_clrset_config16(dev, sci_reg, GSSCIE, SMISCISEL);
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return 0;
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}
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int intel_gma_init_igd_opregion(struct udevice *dev,
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struct igd_opregion *opregion)
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{
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struct optionrom_vbt *vbt = NULL;
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char *vbt_buf;
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int vbt_size;
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int ret;
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ret = locate_vbt(&vbt_buf, &vbt_size);
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if (ret) {
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log_err("GMA: VBT couldn't be found\n");
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return log_msg_ret("find vbt", ret);
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}
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vbt = (struct optionrom_vbt *)vbt_buf;
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memset(opregion, '\0', sizeof(struct igd_opregion));
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memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE,
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sizeof(opregion->header.signature));
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memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild,
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ARRAY_SIZE(vbt->coreblock_biosbuild));
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/* Extended VBT support */
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if (vbt->hdr_vbt_size > sizeof(opregion->vbt.gvd1)) {
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struct optionrom_vbt *ext_vbt;
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ret = bloblist_ensure_size(BLOBLISTT_INTEL_VBT,
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vbt->hdr_vbt_size, 0,
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(void **)&ext_vbt);
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if (ret) {
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log_err("GMA: Unable to add Ext VBT to bloblist\n");
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return log_msg_ret("blob", ret);
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}
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memcpy(ext_vbt, vbt, vbt->hdr_vbt_size);
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opregion->mailbox3.rvda = (uintptr_t)ext_vbt;
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opregion->mailbox3.rvds = vbt->hdr_vbt_size;
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} else {
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/* Raw VBT size which can fit in gvd1 */
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printf("copy to %p\n", opregion->vbt.gvd1);
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memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size);
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}
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/* 8kb */
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opregion->header.size = sizeof(struct igd_opregion) / 1024;
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/*
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* Left-shift version field to accommodate Intel Windows driver quirk
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* when not using a VBIOS.
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* Required for Legacy boot + NGI, UEFI + NGI, and UEFI + GOP driver.
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*
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* No adverse effects when using VBIOS or booting Linux.
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*/
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opregion->header.version = IGD_OPREGION_VERSION << 24;
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/* We just assume we're mobile for now */
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opregion->header.mailboxes = MAILBOXES_MOBILE;
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/* Initialise Mailbox 1 */
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opregion->mailbox1.clid = 1;
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/* Initialise Mailbox 3 */
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opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS;
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opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH;
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opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */
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opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS;
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opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000;
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opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19;
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opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433;
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opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c;
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opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866;
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opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f;
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opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99;
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opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2;
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opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc;
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opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5;
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opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff;
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/* Write ASLS PCI register and prepare SWSCI register */
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ret = intel_gma_opregion_register(dev, (ulong)opregion);
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if (ret)
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return log_msg_ret("write asls", ret);
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return 0;
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}
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