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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
Set up MSRs required for Apollo Lake. This enables Linux to use the timers correctly. Also write the fixed MSRs for this platform. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
328 lines
6.7 KiB
C
328 lines
6.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2014 Google Inc.
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* Copyright (c) 2016 Google, Inc
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* Copyright (C) 2015-2018 Intel Corporation.
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* Copyright (C) 2018 Siemens AG
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* Some code taken from coreboot cpulib.c
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*/
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#include <common.h>
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#include <cpu.h>
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#include <dm.h>
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#include <errno.h>
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#include <log.h>
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#include <acpi/acpigen.h>
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#include <asm/cpu.h>
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#include <asm/cpu_common.h>
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#include <asm/intel_regs.h>
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#include <asm/lapic.h>
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#include <asm/lpc_common.h>
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#include <asm/msr.h>
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#include <asm/mtrr.h>
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#include <asm/post.h>
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#include <asm/microcode.h>
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DECLARE_GLOBAL_DATA_PTR;
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static int report_bist_failure(void)
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{
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if (gd->arch.bist != 0) {
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post_code(POST_BIST_FAILURE);
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printf("BIST failed: %08x\n", gd->arch.bist);
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return -EFAULT;
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}
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return 0;
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}
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int cpu_common_init(void)
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{
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struct udevice *dev, *lpc;
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int ret;
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/* Halt if there was a built in self test failure */
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ret = report_bist_failure();
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if (ret)
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return ret;
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enable_lapic();
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ret = microcode_update_intel();
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if (ret && ret != -EEXIST) {
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debug("%s: Microcode update failure (err=%d)\n", __func__, ret);
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return ret;
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}
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/* Enable upper 128bytes of CMOS */
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writel(1 << 2, RCB_REG(RC));
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/* Early chipset init required before RAM init can work */
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uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
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ret = uclass_first_device(UCLASS_LPC, &lpc);
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if (ret)
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return ret;
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if (!lpc)
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return -ENODEV;
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/* Cause the SATA device to do its early init */
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uclass_first_device(UCLASS_AHCI, &dev);
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return 0;
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}
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int cpu_set_flex_ratio_to_tdp_nominal(void)
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{
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msr_t flex_ratio, msr;
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u8 nominal_ratio;
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/* Check for Flex Ratio support */
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flex_ratio = msr_read(MSR_FLEX_RATIO);
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if (!(flex_ratio.lo & FLEX_RATIO_EN))
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return -EINVAL;
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/* Check for >0 configurable TDPs */
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msr = msr_read(MSR_PLATFORM_INFO);
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if (((msr.hi >> 1) & 3) == 0)
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return -EINVAL;
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/* Use nominal TDP ratio for flex ratio */
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msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
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nominal_ratio = msr.lo & 0xff;
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/* See if flex ratio is already set to nominal TDP ratio */
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if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
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return 0;
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/* Set flex ratio to nominal TDP ratio */
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flex_ratio.lo &= ~0xff00;
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flex_ratio.lo |= nominal_ratio << 8;
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flex_ratio.lo |= FLEX_RATIO_LOCK;
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msr_write(MSR_FLEX_RATIO, flex_ratio);
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/* Set flex ratio in soft reset data register bits 11:6 */
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clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6,
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(nominal_ratio & 0x3f) << 6);
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debug("CPU: Soft reset to set up flex ratio\n");
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/* Set soft reset control to use register value */
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setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
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/* Issue warm reset, will be "CPU only" due to soft reset data */
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outb(0x0, IO_PORT_RESET);
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outb(SYS_RST | RST_CPU, IO_PORT_RESET);
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cpu_hlt();
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/* Not reached */
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return -EINVAL;
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}
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int cpu_intel_get_info(struct cpu_info *info, int bclk)
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{
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msr_t msr;
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msr = msr_read(MSR_IA32_PERF_CTL);
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info->cpu_freq = ((msr.lo >> 8) & 0xff) * bclk * 1000000;
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info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
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1 << CPU_FEAT_UCODE | 1 << CPU_FEAT_DEVICE_ID;
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info->address_width = cpu_phys_address_size();
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return 0;
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}
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int cpu_configure_thermal_target(struct udevice *dev)
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{
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u32 tcc_offset;
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msr_t msr;
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int ret;
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ret = dev_read_u32(dev, "tcc-offset", &tcc_offset);
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if (!ret)
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return -ENOENT;
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/* Set TCC activaiton offset if supported */
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msr = msr_read(MSR_PLATFORM_INFO);
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if (msr.lo & (1 << 30)) {
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msr = msr_read(MSR_TEMPERATURE_TARGET);
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msr.lo &= ~(0xf << 24); /* Bits 27:24 */
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msr.lo |= (tcc_offset & 0xf) << 24;
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msr_write(MSR_TEMPERATURE_TARGET, msr);
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}
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return 0;
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}
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void cpu_set_perf_control(uint clk_ratio)
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{
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msr_t perf_ctl;
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perf_ctl.lo = (clk_ratio & 0xff) << 8;
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perf_ctl.hi = 0;
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msr_write(MSR_IA32_PERF_CTL, perf_ctl);
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debug("CPU: frequency set to %d MHz\n", clk_ratio * INTEL_BCLK_MHZ);
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}
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bool cpu_config_tdp_levels(void)
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{
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msr_t platform_info;
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/* Bits 34:33 indicate how many levels supported */
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platform_info = msr_read(MSR_PLATFORM_INFO);
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return ((platform_info.hi >> 1) & 3) != 0;
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}
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void cpu_set_p_state_to_turbo_ratio(void)
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{
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msr_t msr;
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msr = msr_read(MSR_TURBO_RATIO_LIMIT);
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cpu_set_perf_control(msr.lo);
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}
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enum burst_mode_t cpu_get_burst_mode_state(void)
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{
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enum burst_mode_t state;
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int burst_en, burst_cap;
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msr_t msr;
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uint eax;
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eax = cpuid_eax(0x6);
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burst_cap = eax & 0x2;
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msr = msr_read(MSR_IA32_MISC_ENABLE);
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burst_en = !(msr.hi & BURST_MODE_DISABLE);
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if (!burst_cap && burst_en)
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state = BURST_MODE_UNAVAILABLE;
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else if (burst_cap && !burst_en)
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state = BURST_MODE_DISABLED;
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else if (burst_cap && burst_en)
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state = BURST_MODE_ENABLED;
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else
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state = BURST_MODE_UNKNOWN;
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return state;
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}
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void cpu_set_burst_mode(bool burst_mode)
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{
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msr_t msr;
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msr = msr_read(MSR_IA32_MISC_ENABLE);
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if (burst_mode)
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msr.hi &= ~BURST_MODE_DISABLE;
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else
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msr.hi |= BURST_MODE_DISABLE;
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msr_write(MSR_IA32_MISC_ENABLE, msr);
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}
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void cpu_set_eist(bool eist_status)
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{
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msr_t msr;
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msr = msr_read(MSR_IA32_MISC_ENABLE);
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if (eist_status)
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msr.lo |= MISC_ENABLE_ENHANCED_SPEEDSTEP;
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else
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msr.lo &= ~MISC_ENABLE_ENHANCED_SPEEDSTEP;
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msr_write(MSR_IA32_MISC_ENABLE, msr);
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}
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int cpu_get_coord_type(void)
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{
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return HW_ALL;
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}
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int cpu_get_min_ratio(void)
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{
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msr_t msr;
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/* Get bus ratio limits and calculate clock speeds */
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msr = msr_read(MSR_PLATFORM_INFO);
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return (msr.hi >> 8) & 0xff; /* Max Efficiency Ratio */
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}
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int cpu_get_max_ratio(void)
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{
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u32 ratio_max;
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msr_t msr;
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if (cpu_config_tdp_levels()) {
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/* Set max ratio to nominal TDP ratio */
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msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
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ratio_max = msr.lo & 0xff;
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} else {
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msr = msr_read(MSR_PLATFORM_INFO);
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/* Max Non-Turbo Ratio */
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ratio_max = (msr.lo >> 8) & 0xff;
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}
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return ratio_max;
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}
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int cpu_get_bus_clock_khz(void)
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{
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/*
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* CPU bus clock is set by default here to 100MHz. This function returns
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* the bus clock in KHz.
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*/
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return INTEL_BCLK_MHZ * 1000;
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}
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int cpu_get_power_max(void)
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{
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int power_unit;
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msr_t msr;
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msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
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power_unit = 2 << ((msr.lo & 0xf) - 1);
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msr = msr_read(MSR_PKG_POWER_SKU);
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return (msr.lo & 0x7fff) * 1000 / power_unit;
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}
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int cpu_get_max_turbo_ratio(void)
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{
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msr_t msr;
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msr = msr_read(MSR_TURBO_RATIO_LIMIT);
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return msr.lo & 0xff;
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}
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int cpu_get_cores_per_package(void)
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{
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struct cpuid_result result;
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int cores = 1;
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if (gd->arch.x86_vendor != X86_VENDOR_INTEL)
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return 1;
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result = cpuid_ext(0xb, 1);
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cores = result.ebx & 0xff;
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return cores;
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}
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void cpu_mca_configure(void)
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{
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msr_t msr;
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int i;
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int num_banks;
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msr = msr_read(MSR_IA32_MCG_CAP);
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num_banks = msr.lo & 0xff;
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msr.lo = 0;
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msr.hi = 0;
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for (i = 0; i < num_banks; i++) {
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/* Clear the machine check status */
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msr_write(MSR_IA32_MC0_STATUS + (i * 4), msr);
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/* Initialise machine checks */
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msr_write(MSR_IA32_MC0_CTL + i * 4,
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(msr_t) {.lo = 0xffffffff, .hi = 0xffffffff});
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}
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}
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