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https://github.com/brain-hackers/u-boot-brain
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6571d87315
Set up MSRs required for Apollo Lake. This enables Linux to use the timers correctly. Also write the fixed MSRs for this platform. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
43 lines
975 B
C
43 lines
975 B
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2019 Google LLC
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <asm/cpu_common.h>
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#include <asm/msr.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/iomap.h>
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#include <power/acpi_pmc.h>
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void cpu_flush_l1d_to_l2(void)
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{
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struct msr_t msr;
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msr = msr_read(MSR_POWER_MISC);
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msr.lo |= FLUSH_DL1_L2;
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msr_write(MSR_POWER_MISC, msr);
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}
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void enable_pm_timer_emulation(const struct udevice *pmc)
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{
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struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(pmc);
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msr_t msr;
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/*
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* The derived frequency is calculated as follows:
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* (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
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*
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* Back-solve the multiplier so the 3.579545MHz ACPI timer frequency is
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* used.
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*/
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msr.hi = (3579545ULL << 32) / CTC_FREQ;
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/* Set PM1 timer IO port and enable */
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msr.lo = EMULATE_PM_TMR_EN | (upriv->acpi_base + R_ACPI_PM1_TMR);
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debug("PM timer %x %x\n", msr.hi, msr.lo);
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msr_write(MSR_EMULATE_PM_TIMER, msr);
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}
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