mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-11 12:43:45 +09:00
7a9d109b00
This is in preparation for adapting this board to function correctly on a physical MIPS Malta board. The board is moved into an "imgtec" vendor directory at the same time in order to ready us for any other boards supported by Imagination in the future. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
268 lines
4.9 KiB
ArmAsm
268 lines
4.9 KiB
ArmAsm
/*
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* Startup Code for MIPS32 CPU-core
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*
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* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#ifndef CONFIG_SYS_MIPS_CACHE_MODE
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#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
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#endif
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/*
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* For the moment disable interrupts, mark the kernel mode and
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* set ST0_KX so that the CPU does not spit fire when using
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* 64-bit addresses.
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*/
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.macro setup_c0_status set clr
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.set push
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mfc0 t0, CP0_STATUS
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or t0, ST0_CU0 | \set | 0x1f | \clr
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xor t0, 0x1f | \clr
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mtc0 t0, CP0_STATUS
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.set noreorder
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sll zero, 3 # ehb
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.set pop
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.endm
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.set noreorder
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.globl _start
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.text
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_start:
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/* U-boot entry point */
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b reset
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nop
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.org 0x10
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#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
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/*
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* Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
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* access external NOR flashes. If the board boots from NOR flash the
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* internal BootROM does a blind read at address 0xB0000010 to read the
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* initial configuration for that EBU in order to access the flash
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* device with correct parameters. This config option is board-specific.
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*/
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.word CONFIG_SYS_XWAY_EBU_BOOTCFG
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.word 0x0
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#elif defined(CONFIG_MALTA)
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/*
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* Linux expects the Board ID here.
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*/
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.word 0x00000420 # 0x420 (Malta Board with CoreLV)
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.word 0x00000000
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#endif
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.org 0x200
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/* TLB refill, 32 bit task */
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1: b 1b
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nop
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.org 0x280
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/* XTLB refill, 64 bit task */
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1: b 1b
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nop
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.org 0x300
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/* Cache error exception */
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1: b 1b
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nop
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.org 0x380
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/* General exception */
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1: b 1b
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nop
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.org 0x400
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/* Catch interrupt exceptions */
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1: b 1b
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nop
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.org 0x480
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/* EJTAG debug exception */
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1: b 1b
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nop
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.align 4
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reset:
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/* Clear watch registers */
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mtc0 zero, CP0_WATCHLO
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mtc0 zero, CP0_WATCHHI
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/* WP(Watch Pending), SW0/1 should be cleared */
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mtc0 zero, CP0_CAUSE
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setup_c0_status 0 0
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/* Init Timer */
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mtc0 zero, CP0_COUNT
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mtc0 zero, CP0_COMPARE
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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/* CONFIG0 register */
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li t0, CONF_CM_UNCACHED
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mtc0 t0, CP0_CONFIG
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#endif
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/* Initialize $gp */
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bal 1f
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nop
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.word _gp
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1:
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lw gp, 0(ra)
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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/* Initialize any external memory */
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la t9, lowlevel_init
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jalr t9
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nop
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/* Initialize caches... */
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la t9, mips_cache_reset
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jalr t9
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nop
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/* ... and enable them */
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li t0, CONFIG_SYS_MIPS_CACHE_MODE
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mtc0 t0, CP0_CONFIG
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#endif
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/* Set up temporary stack */
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li sp, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
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la t9, board_init_f
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jr t9
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nop
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/*
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* void relocate_code (addr_sp, gd, addr_moni)
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*
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* This "function" does not return, instead it continues in RAM
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* after relocating the monitor code.
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*
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* a0 = addr_sp
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* a1 = gd
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* a2 = destination address
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*/
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.globl relocate_code
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.ent relocate_code
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relocate_code:
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move sp, a0 # set new stack pointer
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move s0, a1 # save gd in s0
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move s2, a2 # save destination address in s2
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li t0, CONFIG_SYS_MONITOR_BASE
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sub s1, s2, t0 # s1 <-- relocation offset
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la t3, in_ram
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lw t2, -12(t3) # t2 <-- __image_copy_end
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move t1, a2
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add gp, s1 # adjust gp
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/*
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* t0 = source address
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* t1 = target address
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* t2 = source end address
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*/
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1:
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lw t3, 0(t0)
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sw t3, 0(t1)
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addu t0, 4
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blt t0, t2, 1b
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addu t1, 4
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/* If caches were enabled, we would have to flush them here. */
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sub a1, t1, s2 # a1 <-- size
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la t9, flush_cache
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jalr t9
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move a0, s2 # a0 <-- destination address
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/* Jump to where we've relocated ourselves */
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addi t0, s2, in_ram - _start
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jr t0
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nop
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.word __rel_dyn_end
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.word __rel_dyn_start
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.word __image_copy_end
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.word _GLOBAL_OFFSET_TABLE_
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.word num_got_entries
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in_ram:
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/*
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* Now we want to update GOT.
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*
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* GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
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* generated by GNU ld. Skip these reserved entries from relocation.
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*/
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lw t3, -4(t0) # t3 <-- num_got_entries
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lw t8, -8(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
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add t8, s1 # t8 now holds relocated _G_O_T_
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addi t8, t8, 8 # skipping first two entries
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li t2, 2
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1:
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lw t1, 0(t8)
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beqz t1, 2f
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add t1, s1
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sw t1, 0(t8)
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2:
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addi t2, 1
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blt t2, t3, 1b
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addi t8, 4
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/* Update dynamic relocations */
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lw t1, -16(t0) # t1 <-- __rel_dyn_start
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lw t2, -20(t0) # t2 <-- __rel_dyn_end
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b 2f # skip first reserved entry
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addi t1, 8
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1:
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lw t8, -4(t1) # t8 <-- relocation info
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li t3, 3
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bne t8, t3, 2f # skip non R_MIPS_REL32 entries
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nop
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lw t3, -8(t1) # t3 <-- location to fix up in FLASH
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lw t8, 0(t3) # t8 <-- original pointer
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add t8, s1 # t8 <-- adjusted pointer
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add t3, s1 # t3 <-- location to fix up in RAM
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sw t8, 0(t3)
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2:
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blt t1, t2, 1b
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addi t1, 8 # each rel.dyn entry is 8 bytes
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/*
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* Clear BSS
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*
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* GOT is now relocated. Thus __bss_start and __bss_end can be
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* accessed directly via $gp.
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*/
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la t1, __bss_start # t1 <-- __bss_start
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la t2, __bss_end # t2 <-- __bss_end
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1:
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sw zero, 0(t1)
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blt t1, t2, 1b
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addi t1, 4
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move a0, s0 # a0 <-- gd
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la t9, board_init_r
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jr t9
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move a1, s2
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.end relocate_code
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