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https://github.com/brain-hackers/u-boot-brain
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![Marek Vasut](/assets/img/avatar_default.png)
Rework the ULCB CPLD driver and make it into a sysreset driver, since that is what the ULCB CPLD driver is mostly for. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
34 lines
736 B
C
34 lines
736 B
C
/*
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* include/configs/ulcb.h
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* This file is ULCB board configuration.
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*
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* Copyright (C) 2017 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ULCB_H
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#define __ULCB_H
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#undef DEBUG
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#include "rcar-gen3-common.h"
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/* Ethernet RAVB */
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#define CONFIG_BITBANGMII
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#define CONFIG_BITBANGMII_MULTI
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/* Board Clock */
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/* XTAL_CLK : 33.33MHz */
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#define CONFIG_SYS_CLK_FREQ 33333333u
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/* Generic Timer Definitions (use in assembler source) */
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#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
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/* Environment in eMMC, at the end of 2nd "boot sector" */
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#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
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#define CONFIG_SYS_MMC_ENV_DEV 1
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#define CONFIG_SYS_MMC_ENV_PART 2
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#endif /* __ULCB_H */
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