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![Lokesh Vutla](/assets/img/avatar_default.png)
Data manual mentions the new silicon revisions as SR instead of PG. Use the same nomenclature inside U-Boot as well. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
303 lines
7.3 KiB
C
303 lines
7.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* K3: Common Architecture initialization
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*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <spl.h>
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#include "common.h"
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#include <dm.h>
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#include <remoteproc.h>
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#include <linux/soc/ti/ti_sci_protocol.h>
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#include <fdt_support.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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struct ti_sci_handle *get_ti_sci_handle(void)
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{
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struct udevice *dev;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_FIRMWARE,
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DM_GET_DRIVER(ti_sci), &dev);
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if (ret)
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panic("Failed to get SYSFW (%d)\n", ret);
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return (struct ti_sci_handle *)ti_sci_get_handle_from_sysfw(dev);
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}
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_K3_EARLY_CONS
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int early_console_init(void)
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{
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struct udevice *dev;
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int ret;
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gd->baudrate = CONFIG_BAUDRATE;
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ret = uclass_get_device_by_seq(UCLASS_SERIAL, CONFIG_K3_EARLY_CONS_IDX,
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&dev);
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if (ret) {
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printf("Error getting serial dev for early console! (%d)\n",
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ret);
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return ret;
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}
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gd->cur_serial_dev = dev;
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gd->flags |= GD_FLG_SERIAL_READY;
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gd->have_console = 1;
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return 0;
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}
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#endif
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#ifdef CONFIG_SYS_K3_SPL_ATF
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void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
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{
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struct ti_sci_handle *ti_sci = get_ti_sci_handle();
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int ret;
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/* Release all the exclusive devices held by SPL before starting ATF */
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ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
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/*
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* It is assumed that remoteproc device 1 is the corresponding
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* Cortex-A core which runs ATF. Make sure DT reflects the same.
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*/
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ret = rproc_dev_init(1);
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if (ret)
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panic("%s: ATF failed to initialize on rproc (%d)\n", __func__,
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ret);
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ret = rproc_load(1, spl_image->entry_point, 0x200);
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if (ret)
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panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
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/* Add an extra newline to differentiate the ATF logs from SPL */
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printf("Starting ATF on ARM64 core...\n\n");
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ret = rproc_start(1);
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if (ret)
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panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
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debug("Releasing resources...\n");
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release_resources_for_core_shutdown();
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debug("Finalizing core shutdown...\n");
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while (1)
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asm volatile("wfe");
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}
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#endif
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#if defined(CONFIG_OF_LIBFDT)
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int fdt_fixup_msmc_ram(void *blob, char *parent_path, char *node_name)
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{
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u64 msmc_start = 0, msmc_end = 0, msmc_size, reg[2];
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struct ti_sci_handle *ti_sci = get_ti_sci_handle();
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int ret, node, subnode, len, prev_node;
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u32 range[4], addr, size;
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const fdt32_t *sub_reg;
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ti_sci->ops.core_ops.query_msmc(ti_sci, &msmc_start, &msmc_end);
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msmc_size = msmc_end - msmc_start + 1;
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debug("%s: msmc_start = 0x%llx, msmc_size = 0x%llx\n", __func__,
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msmc_start, msmc_size);
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/* find or create "msmc_sram node */
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ret = fdt_path_offset(blob, parent_path);
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if (ret < 0)
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return ret;
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node = fdt_find_or_add_subnode(blob, ret, node_name);
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if (node < 0)
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return node;
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ret = fdt_setprop_string(blob, node, "compatible", "mmio-sram");
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if (ret < 0)
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return ret;
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reg[0] = cpu_to_fdt64(msmc_start);
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reg[1] = cpu_to_fdt64(msmc_size);
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ret = fdt_setprop(blob, node, "reg", reg, sizeof(reg));
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if (ret < 0)
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return ret;
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fdt_setprop_cell(blob, node, "#address-cells", 1);
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fdt_setprop_cell(blob, node, "#size-cells", 1);
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range[0] = 0;
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range[1] = cpu_to_fdt32(msmc_start >> 32);
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range[2] = cpu_to_fdt32(msmc_start & 0xffffffff);
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range[3] = cpu_to_fdt32(msmc_size);
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ret = fdt_setprop(blob, node, "ranges", range, sizeof(range));
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if (ret < 0)
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return ret;
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subnode = fdt_first_subnode(blob, node);
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prev_node = 0;
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/* Look for invalid subnodes and delete them */
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while (subnode >= 0) {
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sub_reg = fdt_getprop(blob, subnode, "reg", &len);
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addr = fdt_read_number(sub_reg, 1);
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sub_reg++;
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size = fdt_read_number(sub_reg, 1);
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debug("%s: subnode = %d, addr = 0x%x. size = 0x%x\n", __func__,
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subnode, addr, size);
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if (addr + size > msmc_size ||
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!strncmp(fdt_get_name(blob, subnode, &len), "sysfw", 5) ||
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!strncmp(fdt_get_name(blob, subnode, &len), "l3cache", 7)) {
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fdt_del_node(blob, subnode);
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debug("%s: deleting subnode %d\n", __func__, subnode);
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if (!prev_node)
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subnode = fdt_first_subnode(blob, node);
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else
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subnode = fdt_next_subnode(blob, prev_node);
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} else {
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prev_node = subnode;
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subnode = fdt_next_subnode(blob, prev_node);
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}
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}
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return 0;
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}
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int fdt_disable_node(void *blob, char *node_path)
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{
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int offs;
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int ret;
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offs = fdt_path_offset(blob, node_path);
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if (offs < 0) {
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printf("Node %s not found.\n", node_path);
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return offs;
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}
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ret = fdt_setprop_string(blob, offs, "status", "disabled");
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if (ret < 0) {
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printf("Could not add status property to node %s: %s\n",
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node_path, fdt_strerror(ret));
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return ret;
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}
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return 0;
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}
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#endif
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#ifndef CONFIG_SYSRESET
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void reset_cpu(ulong ignored)
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{
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}
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#endif
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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u32 soc, rev;
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char *name;
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soc = (readl(CTRLMMR_WKUP_JTAG_DEVICE_ID) &
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DEVICE_ID_FAMILY_MASK) >> DEVICE_ID_FAMILY_SHIFT;
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rev = (readl(CTRLMMR_WKUP_JTAG_ID) &
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JTAG_ID_VARIANT_MASK) >> JTAG_ID_VARIANT_SHIFT;
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printf("SoC: ");
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switch (soc) {
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case AM654:
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name = "AM654";
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break;
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case J721E:
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name = "J721E";
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break;
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default:
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name = "Unknown Silicon";
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};
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printf("%s SR ", name);
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switch (rev) {
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case REV_PG1_0:
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name = "1.0";
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break;
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case REV_PG2_0:
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name = "2.0";
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break;
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default:
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name = "Unknown Revision";
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};
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printf("%s\n", name);
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return 0;
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}
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#endif
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#ifdef CONFIG_ARM64
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void board_prep_linux(bootm_headers_t *images)
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{
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debug("Linux kernel Image start = 0x%lx end = 0x%lx\n",
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images->os.start, images->os.end);
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__asm_flush_dcache_range(images->os.start,
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ROUND(images->os.end,
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CONFIG_SYS_CACHELINE_SIZE));
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}
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#endif
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#ifdef CONFIG_CPU_V7R
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void disable_linefill_optimization(void)
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{
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u32 actlr;
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/*
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* On K3 devices there are 2 conditions where R5F can deadlock:
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* 1.When software is performing series of store operations to
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* cacheable write back/write allocate memory region and later
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* on software execute barrier operation (DSB or DMB). R5F may
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* hang at the barrier instruction.
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* 2.When software is performing a mix of load and store operations
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* within a tight loop and store operations are all writing to
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* cacheable write back/write allocates memory regions, R5F may
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* hang at one of the load instruction.
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*
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* To avoid the above two conditions disable linefill optimization
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* inside Cortex R5F.
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*/
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asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
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actlr |= (1 << 13); /* Set DLFO bit */
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asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
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}
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#endif
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void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
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{
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struct ti_sci_msg_fwl_region region;
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struct ti_sci_fwl_ops *fwl_ops;
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struct ti_sci_handle *ti_sci;
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size_t i, j;
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ti_sci = get_ti_sci_handle();
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fwl_ops = &ti_sci->ops.fwl_ops;
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for (i = 0; i < fwl_data_size; i++) {
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for (j = 0; j < fwl_data[i].regions; j++) {
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region.fwl_id = fwl_data[i].fwl_id;
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region.region = j;
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region.n_permission_regs = 3;
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fwl_ops->get_fwl_region(ti_sci, ®ion);
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if (region.control != 0) {
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pr_debug("Attempting to disable firewall %5d (%25s)\n",
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region.fwl_id, fwl_data[i].name);
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region.control = 0;
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if (fwl_ops->set_fwl_region(ti_sci, ®ion))
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pr_err("Could not disable firewall %5d (%25s)\n",
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region.fwl_id, fwl_data[i].name);
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}
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}
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}
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}
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