Lokesh Vutla b5e01eecc8 ARM: AM43xx: GP_EVM: Add support for DDR3 ... GP EVM has 1GB DDR3 attached(Part no: MT41K512M8RH). Adding details for the same. Below is the brief description of DDR3 init sequence(SW leveling): -> Enable VTT regulator -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program leveling registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>		2013-12-18 21:14:45 -05:00
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board.c	am33xx: Enable D-CACHE on !CONFIG_SYS_DCACHE_OFF	2013-12-12 14:54:12 -05:00
clock_am33xx.c	ARM: AM43xx: clocks: Update DPLL details	2013-12-18 21:14:01 -05:00
clock_am43xx.c	ARM: AM43xx: clocks: Update DPLL details	2013-12-18 21:14:01 -05:00
clock_ti814x.c	Add TI816X support	2013-08-15 18:38:37 -04:00
clock_ti816x.c	Add TI816X support	2013-08-15 18:38:37 -04:00
clock.c	ARM: AM43xx: clocks: Update DPLL details	2013-12-18 21:14:01 -05:00
config.mk	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
ddr.c	ARM: AM43xx: GP_EVM: Add support for DDR3	2013-12-18 21:14:45 -05:00
emif4.c	ARM: AM43xx: EPOS_EVM: Add support for LPDDR2	2013-12-18 21:14:44 -05:00
Makefile	mtd: nand: omap: make am33xx/elm.c as common driver for all OMAPx and AMxxxx platforms	2013-11-21 13:33:41 -06:00
mem.c	am335x: fix GPMC config for NAND and NOR SPL boot	2013-11-21 13:33:41 -06:00
mux.c	am33xx: move generic parts of pinmux handling out from board/ti/am335x	2012-10-25 11:31:37 -07:00
sys_info.c	am335x_evm: am33xx_spl_board_init function and scale core frequency	2013-09-20 16:57:35 -04:00
u-boot-spl.lds	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00