Gabor Juhos 14fdd1a8bf MIPS: start{, 64}.S: fill branch delay slots with NOP instructions ... The romReserved and romExcHandle handlers are accessed by a branch instruction however the delay slots of those instructions are not filled. Because the start.S uses the 'noreorder' directive, the assembler will not fill the delay slots either, and leads to the following assembly code: 0000056c <romReserved>: 56c: 1000ffff b 56c <romReserved> 00000570 <romExcHandle>: 570: 1000ffff b 570 <romExcHandle> In the resulting code, the second branch instruction is placed into the delay slot of the first branch instruction, which is not allowed on the MIPS architecture. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>		2013-01-22 21:09:34 +01:00
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cache.S	MIPS: add board qemu-mips64 support	2012-10-16 15:02:08 +02:00
config.mk	MIPS: add board qemu-mips64 support	2012-10-16 15:02:08 +02:00
cpu.c	MIPS: add board qemu-mips64 support	2012-10-16 15:02:08 +02:00
interrupts.c	MIPS: add board qemu-mips64 support	2012-10-16 15:02:08 +02:00
Makefile	MIPS: add board qemu-mips64 support	2012-10-16 15:02:08 +02:00
start.S	MIPS: start{, 64}.S: fill branch delay slots with NOP instructions	2013-01-22 21:09:34 +01:00
time.c	MIPS: do not initialize timestamp variable before relocate_code	2012-11-25 21:50:43 +01:00