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https://github.com/brain-hackers/u-boot-brain
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14e4b14979
Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
175 lines
3.5 KiB
Plaintext
175 lines
3.5 KiB
Plaintext
/*
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* This device tree is copied from
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* https://raw.githubusercontent.com/torvalds/linux/02440622/arch/arm/boot/dts/
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*/
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#include "skeleton.dtsi"
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/ {
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model = "Aspeed BMC";
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compatible = "aspeed,ast2500";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&vic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,arm1176jzf-s";
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device_type = "cpu";
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reg = <0>;
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};
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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vic: interrupt-controller@1e6c0080 {
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compatible = "aspeed,ast2400-vic";
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interrupt-controller;
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#interrupt-cells = <1>;
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valid-sources = <0xfefff7ff 0x0807ffff>;
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reg = <0x1e6c0080 0x80>;
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};
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clk_clkin: clk_clkin@1e6e2070 {
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#clock-cells = <0>;
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compatible = "aspeed,g5-clkin-clock";
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reg = <0x1e6e2070 0x04>;
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};
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clk_hpll: clk_hpll@1e6e2024 {
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#clock-cells = <0>;
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compatible = "aspeed,g5-hpll-clock";
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reg = <0x1e6e2024 0x4>;
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clocks = <&clk_clkin>;
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};
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clk_ahb: clk_ahb@1e6e2070 {
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#clock-cells = <0>;
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compatible = "aspeed,g5-ahb-clock";
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reg = <0x1e6e2070 0x4>;
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clocks = <&clk_hpll>;
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};
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clk_apb: clk_apb@1e6e2008 {
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#clock-cells = <0>;
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compatible = "aspeed,g5-apb-clock";
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reg = <0x1e6e2008 0x4>;
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clocks = <&clk_hpll>;
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};
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clk_uart: clk_uart@1e6e2008 {
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#clock-cells = <0>;
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compatible = "aspeed,uart-clock";
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reg = <0x1e6e202c 0x4>;
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};
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sram@1e720000 {
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compatible = "mmio-sram";
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reg = <0x1e720000 0x9000>; // 36K
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};
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timer: timer@1e782000 {
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compatible = "aspeed,ast2400-timer";
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reg = <0x1e782000 0x90>;
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// The moxart_timer driver registers only one
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// interrupt and assumes it's for timer 1
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//interrupts = <16 17 18 35 36 37 38 39>;
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interrupts = <16>;
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clocks = <&clk_apb>;
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};
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wdt1: wdt@1e785000 {
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compatible = "aspeed,wdt";
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reg = <0x1e785000 0x1c>;
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interrupts = <27>;
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};
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wdt2: wdt@1e785020 {
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compatible = "aspeed,wdt";
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reg = <0x1e785020 0x1c>;
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interrupts = <27>;
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status = "disabled";
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};
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wdt3: wdt@1e785040 {
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compatible = "aspeed,wdt";
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reg = <0x1e785074 0x1c>;
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status = "disabled";
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};
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uart1: serial@1e783000 {
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compatible = "ns16550a";
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reg = <0x1e783000 0x1000>;
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reg-shift = <2>;
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interrupts = <9>;
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clocks = <&clk_uart>;
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no-loopback-test;
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status = "disabled";
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};
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uart2: serial@1e78d000 {
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compatible = "ns16550a";
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reg = <0x1e78d000 0x1000>;
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reg-shift = <2>;
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interrupts = <32>;
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clocks = <&clk_uart>;
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no-loopback-test;
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status = "disabled";
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};
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uart3: serial@1e78e000 {
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compatible = "ns16550a";
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reg = <0x1e78e000 0x1000>;
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reg-shift = <2>;
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interrupts = <33>;
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clocks = <&clk_uart>;
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no-loopback-test;
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status = "disabled";
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};
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uart4: serial@1e78f000 {
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compatible = "ns16550a";
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reg = <0x1e78f000 0x1000>;
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reg-shift = <2>;
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interrupts = <34>;
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clocks = <&clk_uart>;
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no-loopback-test;
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status = "disabled";
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};
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uart5: serial@1e784000 {
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compatible = "ns16550a";
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reg = <0x1e784000 0x1000>;
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reg-shift = <2>;
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interrupts = <10>;
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clocks = <&clk_uart>;
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current-speed = <38400>;
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no-loopback-test;
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status = "disabled";
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};
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uart6: serial@1e787000 {
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compatible = "ns16550a";
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reg = <0x1e787000 0x1000>;
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reg-shift = <2>;
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interrupts = <10>;
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clocks = <&clk_uart>;
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no-loopback-test;
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status = "disabled";
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};
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};
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};
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};
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