mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 04:36:16 +09:00
14e4b14979
Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
54 lines
889 B
Plaintext
54 lines
889 B
Plaintext
#include <dt-bindings/clock/ast2500-scu.h>
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#include "ast2500.dtsi"
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/ {
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scu: clock-controller@1e6e2000 {
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compatible = "aspeed,ast2500-scu";
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reg = <0x1e6e2000 0x1000>;
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u-boot,dm-pre-reloc;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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sdrammc: sdrammc@1e6e0000 {
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u-boot,dm-pre-reloc;
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compatible = "aspeed,ast2500-sdrammc";
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reg = <0x1e6e0000 0x174
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0x1e6e0200 0x1d4 >;
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clocks = <&scu PLL_MPLL>;
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};
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ahb {
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u-boot,dm-pre-reloc;
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apb {
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u-boot,dm-pre-reloc;
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timer: timer@1e782000 {
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u-boot,dm-pre-reloc;
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};
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uart1: serial@1e783000 {
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clocks = <&scu PCLK_UART1>;
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};
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uart2: serial@1e78d000 {
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clocks = <&scu PCLK_UART2>;
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};
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uart3: serial@1e78e000 {
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clocks = <&scu PCLK_UART3>;
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};
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uart4: serial@1e78f000 {
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clocks = <&scu PCLK_UART4>;
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};
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uart5: serial@1e784000 {
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clocks = <&scu PCLK_UART5>;
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};
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};
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};
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};
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