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https://github.com/brain-hackers/u-boot-brain
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![Wolfgang Denk](/assets/img/avatar_default.png)
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
220 lines
5.6 KiB
C
220 lines
5.6 KiB
C
/*
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* (C) Copyright 2010
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/ppc440.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <i2c.h>
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#include <mtd/cfi_flash.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <asm/4xx_pcie.h>
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#include <asm/ppc4xx-gpio.h>
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int board_early_init_f(void)
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{
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/*
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* Setup the interrupt controller polarities, triggers, etc.
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*/
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mtdcr(UIC0SR, 0xffffffff); /* clear all */
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mtdcr(UIC0ER, 0x00000000); /* disable all */
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mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
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mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
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mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC0SR, 0xffffffff); /* clear all */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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mtdcr(UIC1ER, 0x00000000); /* disable all */
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mtdcr(UIC1CR, 0x00000000); /* all non-critical */
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mtdcr(UIC1PR, 0x7fffffff); /* per ref-board manual */
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mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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mtdcr(UIC2SR, 0xffffffff); /* clear all */
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mtdcr(UIC2ER, 0x00000000); /* disable all */
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mtdcr(UIC2CR, 0x00000000); /* all non-critical */
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mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
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mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC2SR, 0xffffffff); /* clear all */
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mtdcr(UIC3SR, 0xffffffff); /* clear all */
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mtdcr(UIC3ER, 0x00000000); /* disable all */
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mtdcr(UIC3CR, 0x00000000); /* all non-critical */
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mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
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mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
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mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
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mtdcr(UIC3SR, 0xffffffff); /* clear all */
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/*
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* Configure PFC (Pin Function Control) registers
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* enable GPIO 49-63
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* UART0: 4 pins
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*/
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mtsdr(SDR0_PFC0, 0x00007fff);
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mtsdr(SDR0_PFC1, 0x00040000);
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/* Enable PCI host functionality in SDR0_PCI0 */
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mtsdr(SDR0_PCI0, 0xe0000000);
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mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
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/* Setup PLB4-AHB bridge based on the system address map */
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mtdcr(AHB_TOP, 0x8000004B);
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mtdcr(AHB_BOT, 0x8000004B);
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return 0;
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}
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int checkboard(void)
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{
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char buf[64];
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int i = getenv_f("serial#", buf, sizeof(buf));
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printf("Board: T3CORP");
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if (i > 0) {
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puts(", serial# ");
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puts(buf);
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}
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putc('\n');
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return 0;
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}
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int board_early_init_r(void)
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{
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/*
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* T3CORP has 64MBytes of NOR flash (Spansion 29GL512), but the
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* boot EBC mapping only supports a maximum of 16MBytes
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* (4.ff00.0000 - 4.ffff.ffff).
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* To solve this problem, the flash has to get remapped to another
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* EBC address which accepts bigger regions:
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*
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* 0xfn00.0000 -> 4.cn00.0000
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*/
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/* Remap the NOR flash to 0xcn00.0000 ... 0xcfff.ffff */
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mtebc(PB0CR, CONFIG_SYS_FLASH_BASE_PHYS_L | EBC_BXCR_BS_64MB |
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EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT);
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/* Remove TLB entry of boot EBC mapping */
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remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
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/* Add TLB entry for 0xfn00.0000 -> 0x4.cn00.0000 */
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program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE,
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CONFIG_SYS_FLASH_SIZE, TLB_WORD2_I_ENABLE);
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/*
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* Now accessing of the whole 64Mbytes of NOR flash at virtual address
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* 0xfc00.0000 is possible
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*/
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/*
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* Clear potential errors resulting from auto-calibration.
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* If not done, then we could get an interrupt later on when
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* exceptions are enabled.
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*/
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set_mcsr(get_mcsr());
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return 0;
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}
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int misc_init_r(void)
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{
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u32 sdr0_srst1 = 0;
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u32 eth_cfg;
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/*
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* Set EMAC mode/configuration (GMII, SGMII, RGMII...).
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* This is board specific, so let's do it here.
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*/
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mfsdr(SDR0_ETH_CFG, eth_cfg);
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/* disable SGMII mode */
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eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
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SDR0_ETH_CFG_SGMII1_ENABLE |
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SDR0_ETH_CFG_SGMII0_ENABLE);
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/* Set the for 2 RGMII mode */
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/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
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eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
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eth_cfg &= ~SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
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mtsdr(SDR0_ETH_CFG, eth_cfg);
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/*
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* The AHB Bridge core is held in reset after power-on or reset
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* so enable it now
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*/
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mfsdr(SDR0_SRST1, sdr0_srst1);
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sdr0_srst1 &= ~SDR0_SRST1_AHB;
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mtsdr(SDR0_SRST1, sdr0_srst1);
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return 0;
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}
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int board_pcie_last(void)
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{
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/*
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* Only PCIe0 for now, PCIe1 hangs on this board
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*/
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return 0;
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}
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/*
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* Board specific WRDTR and CLKTR values used by the auto-
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* calibration code (4xx_ibm_ddr2_autocalib.c).
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*/
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static struct sdram_timing board_scan_options[] = {
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{1, 2},
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{-1, -1}
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};
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struct sdram_timing *ddr_scan_option(struct sdram_timing *default_val)
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{
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return board_scan_options;
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}
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/*
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* Accessor functions replacing the "weak" functions in
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* drivers/mtd/cfi_flash.c
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*
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* The NOR flash devices "behind" the FPGA's (Xilinx DS617)
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* can only be read correctly in 16bit mode. We need to emulate
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* 8bit and 32bit reads here in the board specific code.
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*/
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u8 flash_read8(void *addr)
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{
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u16 val = __raw_readw((void *)((u32)addr & ~1));
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if ((u32)addr & 1)
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return val;
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return val >> 8;
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}
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u32 flash_read32(void *addr)
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{
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return (__raw_readw(addr) << 16) | __raw_readw((void *)((u32)addr + 2));
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}
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void flash_cmd_reset(flash_info_t *info)
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{
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/*
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* FLASH at address CONFIG_SYS_FLASH_BASE is a Spansion chip and
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* needs the Spansion type reset commands. The other flash chip
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* is located behind a FPGA (Xilinx DS617) and needs the Intel type
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* reset command.
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*/
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if (info->start[0] == CONFIG_SYS_FLASH_BASE)
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flash_write_cmd(info, 0, 0, AMD_CMD_RESET);
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else
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flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
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}
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