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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
Move this function out of common.h and into a relevant header file. Signed-off-by: Simon Glass <sjg@chromium.org>
155 lines
3.8 KiB
C
155 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Synopsys, Inc. All rights reserved.
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <dwmmc.h>
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#include <malloc.h>
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#include <asm/arcregs.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define ARC_PERIPHERAL_BASE 0xF0000000
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#define CGU_ARC_FMEAS_ARC (void *)(ARC_PERIPHERAL_BASE + 0x84)
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#define CGU_ARC_FMEAS_ARC_START BIT(31)
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#define CGU_ARC_FMEAS_ARC_DONE BIT(30)
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#define CGU_ARC_FMEAS_ARC_CNT_MASK GENMASK(14, 0)
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#define CGU_ARC_FMEAS_ARC_RCNT_OFFSET 0
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#define CGU_ARC_FMEAS_ARC_FCNT_OFFSET 15
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#define SDIO_BASE (void *)(ARC_PERIPHERAL_BASE + 0x10000)
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int mach_cpu_init(void)
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{
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int rcnt, fcnt;
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u32 data;
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/* Start frequency measurement */
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writel(CGU_ARC_FMEAS_ARC_START, CGU_ARC_FMEAS_ARC);
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/* Poll DONE bit */
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do {
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data = readl(CGU_ARC_FMEAS_ARC);
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} while (!(data & CGU_ARC_FMEAS_ARC_DONE));
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/* Amount of reference 100 MHz clocks */
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rcnt = ((data >> CGU_ARC_FMEAS_ARC_RCNT_OFFSET) &
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CGU_ARC_FMEAS_ARC_CNT_MASK);
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/* Amount of CPU clocks */
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fcnt = ((data >> CGU_ARC_FMEAS_ARC_FCNT_OFFSET) &
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CGU_ARC_FMEAS_ARC_CNT_MASK);
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gd->cpu_clk = ((100 * fcnt) / rcnt) * 1000000;
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return 0;
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}
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int board_early_init_r(void)
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{
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#define EMSDP_PSRAM_BASE 0xf2001000
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#define PSRAM_FLASH_CONFIG_REG_0 (void *)(EMSDP_PSRAM_BASE + 0x10)
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#define PSRAM_FLASH_CONFIG_REG_1 (void *)(EMSDP_PSRAM_BASE + 0x14)
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#define CRE_ENABLE BIT(31)
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#define CRE_DRIVE_CMD BIT(6)
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#define PSRAM_RCR_DPD BIT(1)
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#define PSRAM_RCR_PAGE_MODE BIT(7)
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/*
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* PSRAM_FLASH_CONFIG_REG_x[30:15] to the address lines[16:1] of flash,
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* thus "<< 1".
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*/
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#define PSRAM_RCR_SETUP ((PSRAM_RCR_DPD | PSRAM_RCR_PAGE_MODE) << 1)
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// Switch PSRAM controller to command mode
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writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_0);
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// Program Refresh Configuration Register (RCR) for BANK0
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writew(0, (void *)(0x10000000 + PSRAM_RCR_SETUP));
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// Switch PSRAM controller back to memory mode
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writel(0, PSRAM_FLASH_CONFIG_REG_0);
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// Switch PSRAM controller to command mode
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writel(CRE_ENABLE | CRE_DRIVE_CMD, PSRAM_FLASH_CONFIG_REG_1);
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// Program Refresh Configuration Register (RCR) for BANK1
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writew(0, (void *)(0x10800000 + PSRAM_RCR_SETUP));
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// Switch PSRAM controller back to memory mode
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writel(0, PSRAM_FLASH_CONFIG_REG_1);
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printf("PSRAM initialized.\n");
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return 0;
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}
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#define CREG_BASE 0xF0001000
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#define CREG_BOOT (void *)(CREG_BASE + 0x0FF0)
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#define CREG_IP_SW_RESET (void *)(CREG_BASE + 0x0FF0)
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#define CREG_IP_VERSION (void *)(CREG_BASE + 0x0FF8)
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/* Bits in CREG_BOOT register */
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#define CREG_BOOT_WP_BIT BIT(8)
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void reset_cpu(ulong addr)
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{
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writel(1, CREG_IP_SW_RESET);
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while (1)
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; /* loop forever till reset */
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}
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static int do_emsdp_rom(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
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{
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u32 creg_boot = readl(CREG_BOOT);
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if (!strcmp(argv[1], "unlock"))
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creg_boot &= ~CREG_BOOT_WP_BIT;
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else if (!strcmp(argv[1], "lock"))
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creg_boot |= CREG_BOOT_WP_BIT;
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else
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return CMD_RET_USAGE;
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writel(creg_boot, CREG_BOOT);
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return CMD_RET_SUCCESS;
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}
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cmd_tbl_t cmd_emsdp[] = {
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U_BOOT_CMD_MKENT(rom, 2, 0, do_emsdp_rom, "", ""),
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};
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static int do_emsdp(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
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{
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cmd_tbl_t *c;
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c = find_cmd_tbl(argv[1], cmd_emsdp, ARRAY_SIZE(cmd_emsdp));
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/* Strip off leading 'emsdp' command */
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argc--;
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argv++;
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if (c == NULL || argc > c->maxargs)
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return CMD_RET_USAGE;
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return c->cmd(cmdtp, flag, argc, argv);
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}
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U_BOOT_CMD(
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emsdp, CONFIG_SYS_MAXARGS, 0, do_emsdp,
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"Synopsys EMSDP specific commands",
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"rom unlock - Unlock non-volatile memory for writing\n"
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"emsdp rom lock - Lock non-volatile memory to prevent writing\n"
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);
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int checkboard(void)
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{
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int version = readl(CREG_IP_VERSION);
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printf("Board: ARC EM Software Development Platform v%d.%d\n",
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(version >> 16) & 0xff, version & 0xff);
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return 0;
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};
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