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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-27 04:18:51 +09:00
![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
421 lines
9.9 KiB
C
421 lines
9.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Keystone2: pll initialization
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clock_defs.h>
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/* DEV and ARM speed definitions as specified in DEVSPEED register */
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int __weak speeds[DEVSPEED_NUMSPDS] = {
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SPD1000,
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SPD1200,
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SPD1350,
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SPD1400,
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SPD1500,
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SPD1400,
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SPD1350,
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SPD1200,
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SPD1000,
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SPD800,
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};
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const struct keystone_pll_regs keystone_pll_regs[] = {
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[CORE_PLL] = {KS2_MAINPLLCTL0, KS2_MAINPLLCTL1},
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[PASS_PLL] = {KS2_PASSPLLCTL0, KS2_PASSPLLCTL1},
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[TETRIS_PLL] = {KS2_ARMPLLCTL0, KS2_ARMPLLCTL1},
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[DDR3A_PLL] = {KS2_DDR3APLLCTL0, KS2_DDR3APLLCTL1},
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[DDR3B_PLL] = {KS2_DDR3BPLLCTL0, KS2_DDR3BPLLCTL1},
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[UART_PLL] = {KS2_UARTPLLCTL0, KS2_UARTPLLCTL1},
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};
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inline void pll_pa_clk_sel(void)
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{
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setbits_le32(keystone_pll_regs[PASS_PLL].reg1, CFG_PLLCTL1_PAPLL_MASK);
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}
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static void wait_for_completion(const struct pll_init_data *data)
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{
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int i;
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for (i = 0; i < 100; i++) {
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sdelay(450);
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if (!(pllctl_reg_read(data->pll, stat) & PLLSTAT_GOSTAT_MASK))
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break;
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}
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}
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static inline void bypass_main_pll(const struct pll_init_data *data)
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{
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pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK |
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PLLCTL_PLLEN_MASK);
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/* 4 cycles of reference clock CLKIN*/
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sdelay(340);
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}
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static void configure_mult_div(const struct pll_init_data *data)
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{
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u32 pllm, plld, bwadj;
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pllm = data->pll_m - 1;
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plld = (data->pll_d - 1) & CFG_PLLCTL0_PLLD_MASK;
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/* Program Multiplier */
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if (data->pll == MAIN_PLL)
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pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK);
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clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
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CFG_PLLCTL0_PLLM_MASK,
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pllm << CFG_PLLCTL0_PLLM_SHIFT);
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/* Program BWADJ */
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bwadj = (data->pll_m - 1) >> 1; /* Divide pllm by 2 */
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clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
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CFG_PLLCTL0_BWADJ_MASK,
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(bwadj << CFG_PLLCTL0_BWADJ_SHIFT) &
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CFG_PLLCTL0_BWADJ_MASK);
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bwadj = bwadj >> CFG_PLLCTL0_BWADJ_BITS;
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clrsetbits_le32(keystone_pll_regs[data->pll].reg1,
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CFG_PLLCTL1_BWADJ_MASK, bwadj);
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/* Program Divider */
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clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
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CFG_PLLCTL0_PLLD_MASK, plld);
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}
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void configure_main_pll(const struct pll_init_data *data)
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{
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u32 tmp, pllod, i, alnctl_val = 0;
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u32 *offset;
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pllod = data->pll_od - 1;
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/* 100 micro sec for stabilization */
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sdelay(210000);
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tmp = pllctl_reg_read(data->pll, secctl);
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/* Check for Bypass */
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if (tmp & SECCTL_BYPASS_MASK) {
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setbits_le32(keystone_pll_regs[data->pll].reg1,
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CFG_PLLCTL1_ENSAT_MASK);
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bypass_main_pll(data);
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/* Powerdown and powerup Main Pll */
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pllctl_reg_setbits(data->pll, secctl, SECCTL_BYPASS_MASK);
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pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK);
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/* 5 micro sec */
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sdelay(21000);
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pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN_MASK);
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} else {
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bypass_main_pll(data);
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}
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configure_mult_div(data);
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/* Program Output Divider */
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pllctl_reg_rmw(data->pll, secctl, SECCTL_OP_DIV_MASK,
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((pllod << SECCTL_OP_DIV_SHIFT) & SECCTL_OP_DIV_MASK));
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/* Program PLLDIVn */
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wait_for_completion(data);
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for (i = 0; i < PLLDIV_MAX; i++) {
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if (i < 3)
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offset = pllctl_reg(data->pll, div1) + i;
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else
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offset = pllctl_reg(data->pll, div4) + (i - 3);
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if (divn_val[i] != -1) {
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__raw_writel(divn_val[i] | PLLDIV_ENABLE_MASK, offset);
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alnctl_val |= BIT(i);
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}
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}
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if (alnctl_val) {
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pllctl_reg_setbits(data->pll, alnctl, alnctl_val);
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/*
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* Set GOSET bit in PLLCMD to initiate the GO operation
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* to change the divide
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*/
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pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GOSTAT_MASK);
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wait_for_completion(data);
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}
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/* Reset PLL */
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pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST_MASK);
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sdelay(21000); /* Wait for a minimum of 7 us*/
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pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST_MASK);
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sdelay(105000); /* Wait for PLL Lock time (min 50 us) */
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/* Enable PLL */
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pllctl_reg_clrbits(data->pll, secctl, SECCTL_BYPASS_MASK);
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pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN_MASK);
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}
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void configure_secondary_pll(const struct pll_init_data *data)
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{
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int pllod = data->pll_od - 1;
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/* Enable Glitch free bypass for ARM PLL */
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if (cpu_is_k2hk() && data->pll == TETRIS_PLL)
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clrbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
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/* Enable Bypass mode */
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setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_ENSAT_MASK);
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setbits_le32(keystone_pll_regs[data->pll].reg0,
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CFG_PLLCTL0_BYPASS_MASK);
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configure_mult_div(data);
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/* Program Output Divider */
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clrsetbits_le32(keystone_pll_regs[data->pll].reg0,
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CFG_PLLCTL0_CLKOD_MASK,
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(pllod << CFG_PLLCTL0_CLKOD_SHIFT) &
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CFG_PLLCTL0_CLKOD_MASK);
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/* Reset PLL */
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setbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);
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/* Wait for 5 micro seconds */
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sdelay(21000);
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/* Select the Output of PASS PLL as input to PASS */
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if (data->pll == PASS_PLL && cpu_is_k2hk())
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pll_pa_clk_sel();
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clrbits_le32(keystone_pll_regs[data->pll].reg1, CFG_PLLCTL1_RST_MASK);
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/* Wait for 500 * REFCLK cucles * (PLLD + 1) */
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sdelay(105000);
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/* Switch to PLL mode */
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clrbits_le32(keystone_pll_regs[data->pll].reg0,
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CFG_PLLCTL0_BYPASS_MASK);
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/* Select the Output of ARM PLL as input to ARM */
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if (cpu_is_k2hk() && data->pll == TETRIS_PLL)
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setbits_le32(KS2_MISC_CTRL, MISC_CTL1_ARM_PLL_EN);
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}
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void init_pll(const struct pll_init_data *data)
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{
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if (data->pll == MAIN_PLL)
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configure_main_pll(data);
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else
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configure_secondary_pll(data);
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/*
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* This is required to provide a delay between multiple
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* consequent PPL configurations
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*/
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sdelay(210000);
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}
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void init_plls(void)
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{
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struct pll_init_data *data;
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int pll;
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for (pll = MAIN_PLL; pll < MAX_PLL_COUNT; pll++) {
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data = get_pll_init_data(pll);
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if (data)
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init_pll(data);
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}
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}
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static int get_max_speed(u32 val, u32 speed_supported, int *spds)
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{
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int speed;
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/* Left most setbit gives the speed */
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for (speed = DEVSPEED_NUMSPDS; speed >= 0; speed--) {
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if ((val & BIT(speed)) & speed_supported)
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return spds[speed];
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}
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/* If no bit is set, return minimum speed */
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if (cpu_is_k2g())
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return SPD200;
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else
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return SPD800;
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}
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static inline u32 read_efuse_bootrom(void)
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{
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if (cpu_is_k2hk() && (cpu_revision() <= 1))
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return __raw_readl(KS2_REV1_DEVSPEED);
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else
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return __raw_readl(KS2_EFUSE_BOOTROM);
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}
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int get_max_arm_speed(int *spds)
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{
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u32 armspeed = read_efuse_bootrom();
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armspeed = (armspeed & DEVSPEED_ARMSPEED_MASK) >>
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DEVSPEED_ARMSPEED_SHIFT;
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return get_max_speed(armspeed, ARM_SUPPORTED_SPEEDS, spds);
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}
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int get_max_dev_speed(int *spds)
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{
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u32 devspeed = read_efuse_bootrom();
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devspeed = (devspeed & DEVSPEED_DEVSPEED_MASK) >>
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DEVSPEED_DEVSPEED_SHIFT;
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return get_max_speed(devspeed, DEV_SUPPORTED_SPEEDS, spds);
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}
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/**
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* pll_freq_get - get pll frequency
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* @pll: pll identifier
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*/
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static unsigned long pll_freq_get(int pll)
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{
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unsigned long mult = 1, prediv = 1, output_div = 2;
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unsigned long ret;
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u32 tmp, reg;
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if (pll == MAIN_PLL) {
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ret = get_external_clk(sys_clk);
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if (pllctl_reg_read(pll, ctl) & PLLCTL_PLLEN_MASK) {
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/* PLL mode */
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tmp = __raw_readl(KS2_MAINPLLCTL0);
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prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1;
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mult = ((tmp & CFG_PLLCTL0_PLLM_HI_MASK) >>
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CFG_PLLCTL0_PLLM_SHIFT |
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(pllctl_reg_read(pll, mult) &
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PLLM_MULT_LO_MASK)) + 1;
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output_div = ((pllctl_reg_read(pll, secctl) &
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SECCTL_OP_DIV_MASK) >>
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SECCTL_OP_DIV_SHIFT) + 1;
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ret = ret / prediv / output_div * mult;
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}
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} else {
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switch (pll) {
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case PASS_PLL:
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ret = get_external_clk(pa_clk);
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reg = KS2_PASSPLLCTL0;
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break;
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case TETRIS_PLL:
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ret = get_external_clk(tetris_clk);
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reg = KS2_ARMPLLCTL0;
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break;
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case DDR3A_PLL:
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ret = get_external_clk(ddr3a_clk);
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reg = KS2_DDR3APLLCTL0;
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break;
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case DDR3B_PLL:
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ret = get_external_clk(ddr3b_clk);
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reg = KS2_DDR3BPLLCTL0;
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break;
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case UART_PLL:
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ret = get_external_clk(uart_clk);
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reg = KS2_UARTPLLCTL0;
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break;
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default:
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return 0;
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}
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tmp = __raw_readl(reg);
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if (!(tmp & CFG_PLLCTL0_BYPASS_MASK)) {
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/* Bypass disabled */
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prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1;
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mult = ((tmp & CFG_PLLCTL0_PLLM_MASK) >>
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CFG_PLLCTL0_PLLM_SHIFT) + 1;
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output_div = ((tmp & CFG_PLLCTL0_CLKOD_MASK) >>
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CFG_PLLCTL0_CLKOD_SHIFT) + 1;
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ret = ((ret / prediv) * mult) / output_div;
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}
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}
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return ret;
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}
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unsigned long ks_clk_get_rate(unsigned int clk)
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{
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unsigned long freq = 0;
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switch (clk) {
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case core_pll_clk:
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freq = pll_freq_get(CORE_PLL);
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break;
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case pass_pll_clk:
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freq = pll_freq_get(PASS_PLL);
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break;
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case tetris_pll_clk:
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if (!cpu_is_k2e())
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freq = pll_freq_get(TETRIS_PLL);
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break;
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case ddr3a_pll_clk:
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freq = pll_freq_get(DDR3A_PLL);
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break;
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case ddr3b_pll_clk:
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if (cpu_is_k2hk())
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freq = pll_freq_get(DDR3B_PLL);
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break;
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case uart_pll_clk:
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if (cpu_is_k2g())
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freq = pll_freq_get(UART_PLL);
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break;
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case sys_clk0_1_clk:
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case sys_clk0_clk:
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freq = pll_freq_get(CORE_PLL) / pll0div_read(1);
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break;
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case sys_clk1_clk:
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return pll_freq_get(CORE_PLL) / pll0div_read(2);
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break;
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case sys_clk2_clk:
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freq = pll_freq_get(CORE_PLL) / pll0div_read(3);
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break;
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case sys_clk3_clk:
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freq = pll_freq_get(CORE_PLL) / pll0div_read(4);
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break;
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case sys_clk0_2_clk:
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freq = ks_clk_get_rate(sys_clk0_clk) / 2;
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break;
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case sys_clk0_3_clk:
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freq = ks_clk_get_rate(sys_clk0_clk) / 3;
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break;
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case sys_clk0_4_clk:
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freq = ks_clk_get_rate(sys_clk0_clk) / 4;
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break;
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case sys_clk0_6_clk:
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freq = ks_clk_get_rate(sys_clk0_clk) / 6;
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break;
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case sys_clk0_8_clk:
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freq = ks_clk_get_rate(sys_clk0_clk) / 8;
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break;
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case sys_clk0_12_clk:
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freq = ks_clk_get_rate(sys_clk0_clk) / 12;
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break;
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case sys_clk0_24_clk:
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freq = ks_clk_get_rate(sys_clk0_clk) / 24;
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break;
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case sys_clk1_3_clk:
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freq = ks_clk_get_rate(sys_clk1_clk) / 3;
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break;
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case sys_clk1_4_clk:
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freq = ks_clk_get_rate(sys_clk1_clk) / 4;
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break;
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case sys_clk1_6_clk:
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freq = ks_clk_get_rate(sys_clk1_clk) / 6;
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break;
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case sys_clk1_12_clk:
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freq = ks_clk_get_rate(sys_clk1_clk) / 12;
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break;
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default:
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break;
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}
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return freq;
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}
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