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https://github.com/brain-hackers/u-boot-brain
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147fd3ac5a
To prepare for the addition of RK3399 HDMI support, the HDMI driver is refactored and broken into a chip-specific and a generic part. This change adds the internal interfaces, makes common/reusable functions externally visible and splits the RK3288 driver into a separate file. For the probing of regulators, we reuse the infrastructure created during the VOP refactoring... i.e. we simply call into the helper function defined for the VOP. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
117 lines
2.7 KiB
C
117 lines
2.7 KiB
C
/*
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* Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <display.h>
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#include <dm.h>
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#include <dw_hdmi.h>
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#include <edid.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/grf_rk3288.h>
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#include <power/regulator.h>
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#include "rk_hdmi.h"
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static int rk3288_hdmi_enable(struct udevice *dev, int panel_bpp,
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const struct display_timing *edid)
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{
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struct rk_hdmi_priv *priv = dev_get_priv(dev);
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struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
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int vop_id = uc_plat->source_id;
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struct rk3288_grf *grf = priv->grf;
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/* hdmi source select hdmi controller */
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rk_setreg(&grf->soc_con6, 1 << 15);
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/* hdmi data from vop id */
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rk_clrsetreg(&grf->soc_con6, 1 << 4, (vop_id == 1) ? (1 << 4) : 0);
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return 0;
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}
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static int rk3288_hdmi_ofdata_to_platdata(struct udevice *dev)
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{
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struct rk_hdmi_priv *priv = dev_get_priv(dev);
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struct dw_hdmi *hdmi = &priv->hdmi;
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hdmi->i2c_clk_high = 0x7a;
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hdmi->i2c_clk_low = 0x8d;
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/*
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* TODO(sjg@chromium.org): The above values don't work - these
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* ones work better, but generate lots of errors in the data.
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*/
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hdmi->i2c_clk_high = 0x0d;
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hdmi->i2c_clk_low = 0x0d;
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return rk_hdmi_ofdata_to_platdata(dev);
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}
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static int rk3288_clk_config(struct udevice *dev)
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{
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struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
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struct clk clk;
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int ret;
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/*
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* Configure the maximum clock to permit whatever resolution the
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* monitor wants
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*/
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ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
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if (ret >= 0) {
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ret = clk_set_rate(&clk, 384000000);
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clk_free(&clk);
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}
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if (ret < 0) {
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debug("%s: Failed to set clock in source device '%s': ret=%d\n",
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__func__, uc_plat->src_dev->name, ret);
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return ret;
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}
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return 0;
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}
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static const char * const rk3288_regulator_names[] = {
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"vcc50_hdmi"
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};
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static int rk3288_hdmi_probe(struct udevice *dev)
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{
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/* Enable VOP clock for RK3288 */
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rk3288_clk_config(dev);
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/* Enable regulators required for HDMI */
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rk_hdmi_probe_regulators(dev, rk3288_regulator_names,
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ARRAY_SIZE(rk3288_regulator_names));
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return rk_hdmi_probe(dev);
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}
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static const struct dm_display_ops rk3288_hdmi_ops = {
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.read_edid = rk_hdmi_read_edid,
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.enable = rk3288_hdmi_enable,
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};
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static const struct udevice_id rk3288_hdmi_ids[] = {
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{ .compatible = "rockchip,rk3288-dw-hdmi" },
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{ }
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};
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U_BOOT_DRIVER(rk3288_hdmi_rockchip) = {
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.name = "rk3288_hdmi_rockchip",
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.id = UCLASS_DISPLAY,
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.of_match = rk3288_hdmi_ids,
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.ops = &rk3288_hdmi_ops,
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.ofdata_to_platdata = rk3288_hdmi_ofdata_to_platdata,
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.probe = rk3288_hdmi_probe,
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.priv_auto_alloc_size = sizeof(struct rk_hdmi_priv),
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};
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