Lukas Auer 1446b26f76 riscv: save hart ID in register tp instead of s0 ... The hart ID passed by the previous boot stage is currently stored in register s0. If we divert the control flow inside a function, which is required as part of multi-hart support, the function epilog may not be called, clobbering register s0. Save the hart ID in the unallocatable register tp instead to protect the hart ID. Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Anup Patel <anup.patel@wdc.com>		2019-04-08 09:44:26 +08:00
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ax25	riscv: move the AX25-specific implementation of flush_dcache_all	2019-01-15 09:36:31 +08:00
generic	riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems	2019-02-27 09:12:33 +08:00
cpu.c	riscv: Do some basic architecture level cpu initialization	2018-12-18 09:56:27 +08:00
Makefile	riscv: Move trap handler codes to mtrap.S	2018-12-18 09:56:27 +08:00
mtrap.S	riscv: Return to previous privilege level after trap handling	2018-12-18 09:56:27 +08:00
start.S	riscv: save hart ID in register tp instead of s0	2019-04-08 09:44:26 +08:00
u-boot.lds	riscv: Make start.S available for all targets	2018-10-03 17:48:14 +08:00