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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
165 lines
3.6 KiB
C
165 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Marek Vasut <marex@denx.de>
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*
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* Based on RAM init sequence by Piotr Dymacz <pepe2k@gmail.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/addrspace.h>
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#include <asm/types.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <mach/ar71xx_regs.h>
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#include <mach/ath79.h>
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DECLARE_GLOBAL_DATA_PTR;
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enum {
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AR934X_SDRAM = 0,
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AR934X_DDR1,
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AR934X_DDR2,
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};
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struct ar934x_mem_config {
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u32 config1;
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u32 config2;
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u32 mode;
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u32 extmode;
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u32 tap;
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};
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static const struct ar934x_mem_config ar934x_mem_config[] = {
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[AR934X_SDRAM] = { 0x7fbe8cd0, 0x959f66a8, 0x33, 0, 0x1f1f },
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[AR934X_DDR1] = { 0x7fd48cd0, 0x99d0e6a8, 0x33, 0, 0x14 },
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[AR934X_DDR2] = { 0xc7d48cd0, 0x9dd0e6a8, 0x33, 0, 0x10012 },
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};
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void ar934x_ddr_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz)
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{
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void __iomem *ddr_regs;
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const struct ar934x_mem_config *memcfg;
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int memtype;
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u32 reg, cycle, ctl;
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ddr_regs = map_physmem(AR71XX_DDR_CTRL_BASE, AR71XX_DDR_CTRL_SIZE,
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MAP_NOCACHE);
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reg = ath79_get_bootstrap();
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if (reg & AR934X_BOOTSTRAP_SDRAM_DISABLED) { /* DDR */
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if (reg & AR934X_BOOTSTRAP_DDR1) { /* DDR 1 */
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memtype = AR934X_DDR1;
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cycle = 0xffff;
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} else { /* DDR 2 */
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memtype = AR934X_DDR2;
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if (gd->arch.rev) {
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ctl = BIT(6); /* Undocumented bit :-( */
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if (reg & BIT(3))
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cycle = 0xff;
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else
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cycle = 0xffff;
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} else {
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/* Force DDR2/x16 configuratio on old chips. */
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ctl = 0;
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cycle = 0xffff; /* DDR2 16bit */
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}
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writel(0xe59, ddr_regs + AR934X_DDR_REG_DDR2_CONFIG);
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udelay(100);
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writel(0x10, ddr_regs + AR71XX_DDR_REG_CONTROL);
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udelay(10);
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writel(0x20, ddr_regs + AR71XX_DDR_REG_CONTROL);
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udelay(10);
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writel(ctl, ddr_regs + AR934X_DDR_REG_CTL_CONF);
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udelay(10);
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}
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} else { /* SDRAM */
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memtype = AR934X_SDRAM;
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cycle = 0xffffffff;
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writel(0x13b, ddr_regs + AR934X_DDR_REG_CTL_CONF);
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udelay(100);
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/* Undocumented register */
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writel(0x13b, ddr_regs + 0x118);
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udelay(100);
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}
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memcfg = &ar934x_mem_config[memtype];
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writel(memcfg->config1, ddr_regs + AR71XX_DDR_REG_CONFIG);
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udelay(100);
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writel(memcfg->config2, ddr_regs + AR71XX_DDR_REG_CONFIG2);
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udelay(100);
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writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);
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udelay(10);
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writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_MODE);
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mdelay(1);
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writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);
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udelay(10);
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if (memtype == AR934X_DDR2) {
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writel(memcfg->mode | 0x100, ddr_regs + AR71XX_DDR_REG_EMR);
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udelay(100);
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writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL);
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udelay(10);
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}
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if (memtype != AR934X_SDRAM)
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writel(0x402, ddr_regs + AR71XX_DDR_REG_EMR);
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udelay(100);
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writel(0x2, ddr_regs + AR71XX_DDR_REG_CONTROL);
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udelay(10);
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writel(0x8, ddr_regs + AR71XX_DDR_REG_CONTROL);
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udelay(10);
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writel(memcfg->mode, ddr_regs + AR71XX_DDR_REG_MODE);
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udelay(100);
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writel(0x1, ddr_regs + AR71XX_DDR_REG_CONTROL);
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udelay(10);
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writel(0x412c /* FIXME */, ddr_regs + AR71XX_DDR_REG_REFRESH);
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udelay(100);
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writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL0);
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writel(memcfg->tap, ddr_regs + AR71XX_DDR_REG_TAP_CTRL1);
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if (memtype != AR934X_SDRAM) {
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if ((gd->arch.rev && (reg & BIT(3))) || !gd->arch.rev) {
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writel(memcfg->tap,
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ddr_regs + AR934X_DDR_REG_TAP_CTRL2);
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writel(memcfg->tap,
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ddr_regs + AR934X_DDR_REG_TAP_CTRL3);
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}
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}
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writel(cycle, ddr_regs + AR71XX_DDR_REG_RD_CYCLE);
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udelay(100);
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writel(0x74444444, ddr_regs + AR934X_DDR_REG_BURST);
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udelay(100);
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writel(0x222, ddr_regs + AR934X_DDR_REG_BURST2);
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udelay(100);
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writel(0xfffff, ddr_regs + AR934X_DDR_REG_TIMEOUT_MAX);
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udelay(100);
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}
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void ddr_tap_tuning(void)
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{
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}
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