Mingkai Hu 13f7988067 armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM latency ... According to design specification, the L2 cache operates at the same frequency as the A72 CPUs in the cluster with a 3-cycle latency, so increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else, will run into different call trace issues. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>		2016-09-14 14:10:02 -07:00
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arm11	ARM: Move SYS_CACHELINE_SIZE over to Kconfig	2016-08-26 17:04:46 -04:00
arm720t	ARM: ARM720t: remove empty asm/arch/hardware.h	2015-04-23 08:52:27 -04:00
arm920t	arm: Allow skipping of low-level init with I-cache on	2016-06-12 23:49:38 +02:00
arm926ejs	ARM: Move SYS_CACHELINE_SIZE over to Kconfig	2016-08-26 17:04:46 -04:00
arm946es	arm: Allow skipping of low-level init with I-cache on	2016-06-12 23:49:38 +02:00
arm1136	common: Pass the boot device into spl_boot_mode()	2016-06-26 20:17:22 +02:00
arm1176	ARM: start.S: fix typo	2016-02-29 14:49:35 -05:00
armv7	nxp: ls102xa: add LS1 PSCI system suspend	2016-09-14 14:08:04 -07:00
armv7m	stm32: Add SDRAM support for stm32f746 discovery board	2016-07-14 18:22:43 -04:00
armv8	armv8: fsl-layerscape: Increase L2 Data RAM latency and L2 Tag RAM latency	2016-09-14 14:10:02 -07:00
pxa	ARM: Move SYS_CACHELINE_SIZE over to Kconfig	2016-08-26 17:04:46 -04:00
sa1100	arm: Allow skipping of low-level init with I-cache on	2016-06-12 23:49:38 +02:00
Makefile	Various Makefiles: Add SPDX-License-Identifier tags	2015-11-10 09:19:52 -05:00
u-boot-spl.lds	spl: arm: Make sure to include all of the u_boot_list entries	2016-03-16 15:27:55 -04:00
u-boot.lds	ARM: armv7: guard memory reserve for PSCI with #ifdef CONFIG_ARMV7_PSCI	2016-09-07 08:48:46 -04:00