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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
We will use a system controller to model the Intel Management Engine. Enable this for link. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
51 lines
1.1 KiB
Plaintext
51 lines
1.1 KiB
Plaintext
CONFIG_X86=y
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CONFIG_SYS_MALLOC_F_LEN=0x1800
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CONFIG_DM_I2C=y
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CONFIG_VENDOR_GOOGLE=y
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CONFIG_DEFAULT_DEVICE_TREE="chromebook_link"
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CONFIG_TARGET_CHROMEBOOK_LINK=y
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CONFIG_HAVE_MRC=y
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CONFIG_ENABLE_MRC_CACHE=y
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CONFIG_SMP=y
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CONFIG_HAVE_VGA_BIOS=y
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CONFIG_CMD_CPU=y
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_GPIO=y
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# CONFIG_CMD_SETEXPR is not set
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# CONFIG_CMD_NFS is not set
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CONFIG_BOOTSTAGE=y
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CONFIG_BOOTSTAGE_REPORT=y
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CONFIG_CMD_BOOTSTAGE=y
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CONFIG_CMD_TPM=y
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CONFIG_CMD_TPM_TEST=y
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CONFIG_OF_CONTROL=y
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CONFIG_REGMAP=y
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CONFIG_SYSCON=y
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CONFIG_CPU=y
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CONFIG_SYS_I2C_INTEL=y
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CONFIG_CMD_CROS_EC=y
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CONFIG_CROS_EC=y
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CONFIG_CROS_EC_LPC=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_GIGADEVICE=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_WINBOND=y
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CONFIG_DM_PCI=y
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CONFIG_DM_RTC=y
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CONFIG_DEBUG_UART=y
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CONFIG_DEBUG_UART_BASE=0x3f8
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CONFIG_DEBUG_UART_CLOCK=1843200
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CONFIG_DEBUG_UART_BOARD_INIT=y
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CONFIG_SYS_NS16550=y
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CONFIG_ICH_SPI=y
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CONFIG_TIMER=y
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CONFIG_TPM_TIS_LPC=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_VIDEO_VESA=y
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CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
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CONFIG_FRAMEBUFFER_VESA_MODE_11A=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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CONFIG_TPM=y
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