mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 19:56:18 +09:00
6b20dc165e
This fixes a problem, where booting Linux using distro boot will sometimes lead to an invalid instruction exception on the main hart. The secondary harts are not affected and boot Linux successfully. The root cause of this problem is a stack overflow on the main hart. With distro boot, the current default stack size of 8KiB on RISC-V is not sufficient and will cause a stack overflow. The stacks are allocated sequentially. In the case of a stack overflow the stack of the main hart can reach into that of another hart and be corrupted. The stack overflow previously did not cause any problems, because only stack frames, which are not used anymore since the hart enters Linux, were corrupted. Starting with GCC 9, the stack usage has decreased. Now, only the most recent stack frame overflows into the stack of a secondary hart and is corrupted. The illegal instruction exception is caused by the secondary hart overwriting the return address in the stack frame of the main hart with an address that does not include valid code. Increase the default stack size of each hart to 16KiB to avoid this problem. Reported-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Tested-by: David Abdurachmanov <david.abdurachmanov@sifive.com> Tested-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Rick Chen <rick@andestech.com>
233 lines
4.9 KiB
Plaintext
233 lines
4.9 KiB
Plaintext
menu "RISC-V architecture"
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depends on RISCV
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config SYS_ARCH
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default "riscv"
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choice
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prompt "Target select"
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optional
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config TARGET_AX25_AE350
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bool "Support ax25-ae350"
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config TARGET_MICROCHIP_ICICLE
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bool "Support Microchip PolarFire-SoC Icicle Board"
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config TARGET_QEMU_VIRT
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bool "Support QEMU Virt Board"
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config TARGET_SIFIVE_FU540
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bool "Support SiFive FU540 Board"
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endchoice
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config SYS_ICACHE_OFF
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bool "Do not enable icache"
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default n
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help
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Do not enable instruction cache in U-Boot.
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config SPL_SYS_ICACHE_OFF
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bool "Do not enable icache in SPL"
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depends on SPL
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default SYS_ICACHE_OFF
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help
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Do not enable instruction cache in SPL.
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config SYS_DCACHE_OFF
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bool "Do not enable dcache"
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default n
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help
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Do not enable data cache in U-Boot.
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config SPL_SYS_DCACHE_OFF
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bool "Do not enable dcache in SPL"
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depends on SPL
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default SYS_DCACHE_OFF
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help
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Do not enable data cache in SPL.
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# board-specific options below
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source "board/AndesTech/ax25-ae350/Kconfig"
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source "board/emulation/qemu-riscv/Kconfig"
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source "board/microchip/mpfs_icicle/Kconfig"
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source "board/sifive/fu540/Kconfig"
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# platform-specific options below
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source "arch/riscv/cpu/ax25/Kconfig"
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source "arch/riscv/cpu/generic/Kconfig"
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# architecture-specific options below
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choice
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prompt "Base ISA"
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default ARCH_RV32I
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config ARCH_RV32I
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bool "RV32I"
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select 32BIT
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help
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Choose this option to target the RV32I base integer instruction set.
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config ARCH_RV64I
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bool "RV64I"
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select 64BIT
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select PHYS_64BIT
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help
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Choose this option to target the RV64I base integer instruction set.
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endchoice
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choice
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prompt "Code Model"
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default CMODEL_MEDLOW
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config CMODEL_MEDLOW
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bool "medium low code model"
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help
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U-Boot and its statically defined symbols must lie within a single 2 GiB
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address range and must lie between absolute addresses -2 GiB and +2 GiB.
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config CMODEL_MEDANY
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bool "medium any code model"
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help
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U-Boot and its statically defined symbols must be within any single 2 GiB
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address range.
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endchoice
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choice
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prompt "Run Mode"
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default RISCV_MMODE
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config RISCV_MMODE
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bool "Machine"
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help
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Choose this option to build U-Boot for RISC-V M-Mode.
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config RISCV_SMODE
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bool "Supervisor"
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help
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Choose this option to build U-Boot for RISC-V S-Mode.
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endchoice
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choice
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prompt "SPL Run Mode"
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default SPL_RISCV_MMODE
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depends on SPL
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config SPL_RISCV_MMODE
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bool "Machine"
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help
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Choose this option to build U-Boot SPL for RISC-V M-Mode.
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config SPL_RISCV_SMODE
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bool "Supervisor"
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help
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Choose this option to build U-Boot SPL for RISC-V S-Mode.
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endchoice
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config RISCV_ISA_C
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bool "Emit compressed instructions"
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default y
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help
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Adds "C" to the ISA subsets that the toolchain is allowed to emit
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when building U-Boot, which results in compressed instructions in the
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U-Boot binary.
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config RISCV_ISA_A
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def_bool y
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config 32BIT
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bool
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config 64BIT
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bool
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config SIFIVE_CLINT
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bool
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depends on RISCV_MMODE || SPL_RISCV_MMODE
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select REGMAP
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select SYSCON
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select SPL_REGMAP if SPL
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select SPL_SYSCON if SPL
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help
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The SiFive CLINT block holds memory-mapped control and status registers
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associated with software and timer interrupts.
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config ANDES_PLIC
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bool
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depends on RISCV_MMODE || SPL_RISCV_MMODE
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select REGMAP
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select SYSCON
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select SPL_REGMAP if SPL
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select SPL_SYSCON if SPL
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help
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The Andes PLIC block holds memory-mapped claim and pending registers
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associated with software interrupt.
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config ANDES_PLMT
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bool
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depends on RISCV_MMODE || SPL_RISCV_MMODE
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select REGMAP
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select SYSCON
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select SPL_REGMAP if SPL
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select SPL_SYSCON if SPL
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help
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The Andes PLMT block holds memory-mapped mtime register
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associated with timer tick.
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config RISCV_RDTIME
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bool
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default y if RISCV_SMODE || SPL_RISCV_SMODE
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help
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The provides the riscv_get_time() API that is implemented using the
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standard rdtime instruction. This is the case for S-mode U-Boot, and
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is useful for processors that support rdtime in M-mode too.
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config SYS_MALLOC_F_LEN
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default 0x1000
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config SMP
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bool "Symmetric Multi-Processing"
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help
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This enables support for systems with more than one CPU. If
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you say N here, U-Boot will run on single and multiprocessor
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machines, but will use only one CPU of a multiprocessor
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machine. If you say Y here, U-Boot will run on many, but not
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all, single processor machines.
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config NR_CPUS
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int "Maximum number of CPUs (2-32)"
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range 2 32
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depends on SMP
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default 8
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help
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On multiprocessor machines, U-Boot sets up a stack for each CPU.
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Stack memory is pre-allocated. U-Boot must therefore know the
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maximum number of CPUs that may be present.
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config SBI_IPI
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bool
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default y if RISCV_SMODE || SPL_RISCV_SMODE
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depends on SMP
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config XIP
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bool "XIP mode"
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help
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XIP (eXecute In Place) is a method for executing code directly
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from a NOR flash memory without copying the code to ram.
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Say yes here if U-Boot boots from flash directly.
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config STACK_SIZE_SHIFT
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int
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default 14
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config SPL_LDSCRIPT
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default "arch/riscv/cpu/u-boot-spl.lds"
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endmenu
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