mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
410 lines
10 KiB
C
410 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* clock_ti814x.c
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*
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* Clocks for TI814X based boards
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*
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* Copyright (C) 2013, Texas Instruments, Incorporated
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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/* PRCM */
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#define PRCM_MOD_EN 0x2
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/* CLK_SRC */
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#define OSC_SRC0 0
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#define OSC_SRC1 1
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#define L3_OSC_SRC OSC_SRC0
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#define OSC_0_FREQ 20
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#define DCO_HS2_MIN 500
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#define DCO_HS2_MAX 1000
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#define DCO_HS1_MIN 1000
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#define DCO_HS1_MAX 2000
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#define SELFREQDCO_HS2 0x00000801
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#define SELFREQDCO_HS1 0x00001001
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#define MPU_N 0x1
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#define MPU_M 0x3C
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#define MPU_M2 1
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#define MPU_CLKCTRL 0x1
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#define L3_N 19
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#define L3_M 880
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#define L3_M2 4
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#define L3_CLKCTRL 0x801
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#define DDR_N 19
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#define DDR_M 666
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#define DDR_M2 2
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#define DDR_CLKCTRL 0x801
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/* ADPLLJ register values */
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#define ADPLLJ_CLKCTRL_HS2 0x00000801 /* HS2 mode, TINT2 = 1 */
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#define ADPLLJ_CLKCTRL_HS1 0x00001001 /* HS1 mode, TINT2 = 1 */
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#define ADPLLJ_CLKCTRL_CLKDCOLDOEN (1 << 29)
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#define ADPLLJ_CLKCTRL_IDLE (1 << 23)
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#define ADPLLJ_CLKCTRL_CLKOUTEN (1 << 20)
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#define ADPLLJ_CLKCTRL_CLKOUTLDOEN (1 << 19)
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#define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ (1 << 17)
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#define ADPLLJ_CLKCTRL_LPMODE (1 << 12)
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#define ADPLLJ_CLKCTRL_DRIFTGUARDIAN (1 << 11)
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#define ADPLLJ_CLKCTRL_REGM4XEN (1 << 10)
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#define ADPLLJ_CLKCTRL_TINITZ (1 << 0)
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#define ADPLLJ_CLKCTRL_CLKDCO (ADPLLJ_CLKCTRL_CLKDCOLDOEN | \
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ADPLLJ_CLKCTRL_CLKOUTEN | \
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ADPLLJ_CLKCTRL_CLKOUTLDOEN | \
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ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ)
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#define ADPLLJ_STATUS_PHASELOCK (1 << 10)
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#define ADPLLJ_STATUS_FREQLOCK (1 << 9)
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#define ADPLLJ_STATUS_PHSFRQLOCK (ADPLLJ_STATUS_PHASELOCK | \
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ADPLLJ_STATUS_FREQLOCK)
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#define ADPLLJ_STATUS_BYPASSACK (1 << 8)
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#define ADPLLJ_STATUS_BYPASS (1 << 0)
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#define ADPLLJ_STATUS_BYPASSANDACK (ADPLLJ_STATUS_BYPASSACK | \
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ADPLLJ_STATUS_BYPASS)
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#define ADPLLJ_TENABLE_ENB (1 << 0)
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#define ADPLLJ_TENABLEDIV_ENB (1 << 0)
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#define ADPLLJ_M2NDIV_M2SHIFT 16
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#define MPU_PLL_BASE (PLL_SUBSYS_BASE + 0x048)
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#define L3_PLL_BASE (PLL_SUBSYS_BASE + 0x110)
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#define DDR_PLL_BASE (PLL_SUBSYS_BASE + 0x290)
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struct ad_pll {
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unsigned int pwrctrl;
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unsigned int clkctrl;
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unsigned int tenable;
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unsigned int tenablediv;
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unsigned int m2ndiv;
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unsigned int mn2div;
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unsigned int fracdiv;
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unsigned int bwctrl;
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unsigned int fracctrl;
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unsigned int status;
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unsigned int m3div;
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unsigned int rampctrl;
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};
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#define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0)
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#define ENET_CLKCTRL_CMPL 0x30000
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#define SATA_PLL_BASE (CTRL_BASE + 0x0720)
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struct sata_pll {
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unsigned int pllcfg0;
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unsigned int pllcfg1;
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unsigned int pllcfg2;
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unsigned int pllcfg3;
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unsigned int pllcfg4;
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unsigned int pllstatus;
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unsigned int rxstatus;
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unsigned int txstatus;
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unsigned int testcfg;
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};
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#define SEL_IN_FREQ (0x1 << 31)
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#define DIGCLRZ (0x1 << 30)
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#define ENDIGLDO (0x1 << 4)
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#define APLL_CP_CURR (0x1 << 3)
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#define ENBGSC_REF (0x1 << 2)
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#define ENPLLLDO (0x1 << 1)
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#define ENPLL (0x1 << 0)
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#define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF)
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#define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF)
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#define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO)
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#define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \
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ENPLLLDO | ENPLL)
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#define PLL_LOCK (0x1 << 0)
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#define ENSATAMODE (0x1 << 31)
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#define PLLREFSEL (0x1 << 30)
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#define MDIVINT (0x4b << 18)
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#define EN_CLKAUX (0x1 << 5)
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#define EN_CLK125M (0x1 << 4)
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#define EN_CLK100M (0x1 << 3)
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#define EN_CLK50M (0x1 << 2)
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#define SATA_PLLCFG1 (ENSATAMODE | \
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PLLREFSEL | \
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MDIVINT | \
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EN_CLKAUX | \
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EN_CLK125M | \
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EN_CLK100M | \
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EN_CLK50M)
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#define DIGLDO_EN_CAPLESSMODE (0x1 << 22)
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#define PLLDO_EN_LDO_STABLE (0x1 << 11)
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#define PLLDO_EN_BUF_CUR (0x1 << 7)
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#define PLLDO_EN_LP (0x1 << 6)
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#define PLLDO_CTRL_TRIM_1_4V (0x10 << 1)
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#define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE | \
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PLLDO_EN_LDO_STABLE | \
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PLLDO_EN_BUF_CUR | \
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PLLDO_EN_LP | \
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PLLDO_CTRL_TRIM_1_4V)
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const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
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const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
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const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
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/*
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* Enable the peripheral clock for required peripherals
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*/
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static void enable_per_clocks(void)
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{
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/* HSMMC1 */
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writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
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while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
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;
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/* Ethernet */
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writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
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writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
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while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0)
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;
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writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
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while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)
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;
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/* RTC clocks */
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writel(PRCM_MOD_EN, &cmalwon->rtcclkstctrl);
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writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl);
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while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN)
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;
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}
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/*
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* select the HS1 or HS2 for DCO Freq
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* return : CLKCTRL
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*/
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static u32 pll_dco_freq_sel(u32 clkout_dco)
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{
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if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX)
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return SELFREQDCO_HS2;
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else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX)
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return SELFREQDCO_HS1;
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else
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return -1;
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}
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/*
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* select the sigma delta config
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* return: sigma delta val
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*/
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static u32 pll_sigma_delta_val(u32 clkout_dco)
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{
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u32 sig_val = 0;
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sig_val = (clkout_dco + 225) / 250;
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sig_val = sig_val << 24;
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return sig_val;
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}
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/*
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* configure individual ADPLLJ
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*/
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static void pll_config(u32 base, u32 n, u32 m, u32 m2,
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u32 clkctrl_val, int adpllj)
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{
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const struct ad_pll *adpll = (struct ad_pll *)base;
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u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0;
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u32 sig_val = 0, hs_mod = 0;
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m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n;
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mn2val = m;
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/* calculate clkout_dco */
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clkout_dco = ((OSC_0_FREQ / (n+1)) * m);
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/* sigma delta & Hs mode selection skip for ADPLLS*/
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if (adpllj) {
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sig_val = pll_sigma_delta_val(clkout_dco);
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hs_mod = pll_dco_freq_sel(clkout_dco);
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}
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/* by-pass pll */
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read_clkctrl = readl(&adpll->clkctrl);
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writel((read_clkctrl | ADPLLJ_CLKCTRL_IDLE), &adpll->clkctrl);
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while ((readl(&adpll->status) & ADPLLJ_STATUS_BYPASSANDACK)
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!= ADPLLJ_STATUS_BYPASSANDACK)
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;
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/* clear TINITZ */
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read_clkctrl = readl(&adpll->clkctrl);
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writel((read_clkctrl & ~ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
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/*
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* ref_clk = 20/(n + 1);
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* clkout_dco = ref_clk * m;
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* clk_out = clkout_dco/m2;
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*/
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read_clkctrl = readl(&adpll->clkctrl) &
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~(ADPLLJ_CLKCTRL_LPMODE |
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ADPLLJ_CLKCTRL_DRIFTGUARDIAN |
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ADPLLJ_CLKCTRL_REGM4XEN);
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writel(m2nval, &adpll->m2ndiv);
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writel(mn2val, &adpll->mn2div);
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/* Skip for modena(ADPLLS) */
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if (adpllj) {
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writel(sig_val, &adpll->fracdiv);
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writel((read_clkctrl | hs_mod), &adpll->clkctrl);
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}
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/* Load M2, N2 dividers of ADPLL */
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writel(ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
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writel(~ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
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/* Load M, N dividers of ADPLL */
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writel(ADPLLJ_TENABLE_ENB, &adpll->tenable);
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writel(~ADPLLJ_TENABLE_ENB, &adpll->tenable);
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/* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */
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read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_CLKDCO;
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if (adpllj)
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writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO),
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&adpll->clkctrl);
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/* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */
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read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_IDLE;
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writel((read_clkctrl | ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
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/* Wait for phase and freq lock */
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while ((readl(&adpll->status) & ADPLLJ_STATUS_PHSFRQLOCK) !=
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ADPLLJ_STATUS_PHSFRQLOCK)
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;
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}
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static void unlock_pll_control_mmr(void)
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{
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/* TRM 2.10.1.4 and 3.2.7-3.2.11 */
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writel(0x1EDA4C3D, 0x481C5040);
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writel(0x2FF1AC2B, 0x48140060);
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writel(0xF757FDC0, 0x48140064);
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writel(0xE2BC3A6D, 0x48140068);
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writel(0x1EBF131D, 0x4814006c);
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writel(0x6F361E05, 0x48140070);
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}
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static void mpu_pll_config(void)
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{
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pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0);
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}
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static void l3_pll_config(void)
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{
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u32 l3_osc_src, rd_osc_src = 0;
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l3_osc_src = L3_OSC_SRC;
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rd_osc_src = readl(OSC_SRC_CTRL);
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if (OSC_SRC0 == l3_osc_src)
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writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL);
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else
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writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL);
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pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1);
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}
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void ddr_pll_config(unsigned int ddrpll_m)
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{
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pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1);
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}
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void sata_pll_config(void)
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{
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/*
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* This sequence for configuring the SATA PLL
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* resident in the control module is documented
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* in TI8148 TRM section 21.3.1
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*/
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writel(SATA_PLLCFG1, &spll->pllcfg1);
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udelay(50);
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writel(SATA_PLLCFG3, &spll->pllcfg3);
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udelay(50);
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writel(SATA_PLLCFG0_1, &spll->pllcfg0);
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udelay(50);
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writel(SATA_PLLCFG0_2, &spll->pllcfg0);
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udelay(50);
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writel(SATA_PLLCFG0_3, &spll->pllcfg0);
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udelay(50);
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writel(SATA_PLLCFG0_4, &spll->pllcfg0);
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udelay(50);
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while (((readl(&spll->pllstatus) & PLL_LOCK) == 0))
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;
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}
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void enable_dmm_clocks(void)
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{
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writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
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writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
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writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
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while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN)
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;
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writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
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while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN)
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;
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while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
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;
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writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
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while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN)
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;
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writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
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while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
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;
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}
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void setup_clocks_for_console(void)
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{
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unlock_pll_control_mmr();
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/* UART0 */
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writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
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while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
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;
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}
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void setup_early_clocks(void)
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{
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setup_clocks_for_console();
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}
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/*
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* Configure the PLL/PRCM for necessary peripherals
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*/
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void prcm_init(void)
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{
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/* Enable the control module */
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writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
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/* Configure PLLs */
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mpu_pll_config();
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l3_pll_config();
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sata_pll_config();
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/* Enable the required peripherals */
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enable_per_clocks();
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}
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