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![Bibek Basu](/assets/img/avatar_default.png)
RAM repair has a few pre-requisites: 1) PMIC power supply (rail) enabled. 2) PMC CRAIL power partition powered. 3) Fuse clock active (it's the default). 4) PLLP reshift branch enabled (it's the default, when PLLP is active). RAM repair also only need run whenever specific partitions are powered (main SoC and CCPLEX respectively); RAM repair does not need to be triggered when any other partition changes state. start_cpu() needs to be re-ordered slightly to match these requirements. Note that C0NC and CE0 aren't required for RAM repair to operate, but they also do no harm, so the entire of powerup_cpus() is moved rather than splitting it up. The call to remove_cpu_resets() is moved last to ensure that all other actions complete before releasing reset; since the PMC power partitions are now enabled early, releasing reset is what causes the CPUs to start executing code, and RAM repair must complete before the CPU boots. Note that this commit is the result of squashing a numbmer of commits in NVIDIA's downstream L4T branch, hence the multiple signoffs below. Signed-off-by: Bibek Basu <bbasu@nvidia.com> Signed-off-by: Sandipan Patra <spatra@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
56 lines
1.5 KiB
C
56 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010-2013
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#ifndef _TEGRA124_FLOW_H_
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#define _TEGRA124_FLOW_H_
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struct flow_ctlr {
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u32 halt_cpu_events; /* offset 0x00 */
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u32 halt_cop_events; /* offset 0x04 */
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u32 cpu_csr; /* offset 0x08 */
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u32 cop_csr; /* offset 0x0c */
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u32 xrq_events; /* offset 0x10 */
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u32 halt_cpu1_events; /* offset 0x14 */
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u32 cpu1_csr; /* offset 0x18 */
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u32 halt_cpu2_events; /* offset 0x1c */
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u32 cpu2_csr; /* offset 0x20 */
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u32 halt_cpu3_events; /* offset 0x24 */
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u32 cpu3_csr; /* offset 0x28 */
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u32 cluster_control; /* offset 0x2c */
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u32 halt_cop1_events; /* offset 0x30 */
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u32 halt_cop1_csr; /* offset 0x34 */
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u32 cpu_pwr_csr; /* offset 0x38 */
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u32 mpid; /* offset 0x3c */
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u32 ram_repair; /* offset 0x40 */
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u32 flow_dbg_sel; /* offset 0x44 */
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u32 flow_dbg_cnt0; /* offset 0x48 */
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u32 flow_dbg_cnt1; /* offset 0x4c */
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u32 flow_dbg_qual; /* offset 0x50 */
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u32 flow_ctrl_spare; /* offset 0x54 */
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u32 ram_repair_cluster1;/* offset 0x58 */
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};
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/* HALT_COP_EVENTS_0, 0x04 */
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#define EVENT_MSEC (1 << 24)
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#define EVENT_USEC (1 << 25)
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#define EVENT_JTAG (1 << 28)
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#define EVENT_MODE_STOP (2 << 29)
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/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
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#define ACTIVE_LP (1 << 0)
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/* CPUn_CSR_0 */
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#define CSR_ENABLE (1 << 0)
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#define CSR_IMMEDIATE_WAKE (1 << 3)
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#define CSR_WAIT_WFI_SHIFT 8
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#define CSR_PWR_OFF_STS (1 << 16)
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#define RAM_REPAIR_REQ BIT(0)
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#define RAM_REPAIR_STS BIT(1)
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#define RAM_REPAIR_BYPASS_EN BIT(2)
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#endif /* _TEGRA124_FLOW_H_ */
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