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![Simon Glass](/assets/img/avatar_default.png)
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
211 lines
5.7 KiB
C
211 lines
5.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* TI serdes driver for keystone2.
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*
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* (C) Copyright 2014
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* Texas Instruments Incorporated, <www.ti.com>
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*/
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#include <errno.h>
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#include <common.h>
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#include <asm/ti-common/keystone_serdes.h>
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#include <linux/bitops.h>
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#define SERDES_CMU_REGS(x) (0x0000 + (0x0c00 * (x)))
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#define SERDES_LANE_REGS(x) (0x0200 + (0x200 * (x)))
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#define SERDES_COMLANE_REGS 0x0a00
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#define SERDES_WIZ_REGS 0x1fc0
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#define SERDES_CMU_REG_000(x) (SERDES_CMU_REGS(x) + 0x000)
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#define SERDES_CMU_REG_010(x) (SERDES_CMU_REGS(x) + 0x010)
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#define SERDES_COMLANE_REG_000 (SERDES_COMLANE_REGS + 0x000)
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#define SERDES_LANE_REG_000(x) (SERDES_LANE_REGS(x) + 0x000)
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#define SERDES_LANE_REG_028(x) (SERDES_LANE_REGS(x) + 0x028)
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#define SERDES_LANE_CTL_STATUS_REG(x) (SERDES_WIZ_REGS + 0x0020 + (4 * (x)))
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#define SERDES_PLL_CTL_REG (SERDES_WIZ_REGS + 0x0034)
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#define SERDES_RESET BIT(28)
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#define SERDES_LANE_RESET BIT(29)
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#define SERDES_LANE_LOOPBACK BIT(30)
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#define SERDES_LANE_EN_VAL(x, y, z) (x[y] | (z << 26) | (z << 10))
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#define SERDES_CMU_CFG_NUM 5
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#define SERDES_COMLANE_CFG_NUM 10
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#define SERDES_LANE_CFG_NUM 10
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struct serdes_cfg {
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u32 ofs;
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u32 val;
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u32 mask;
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};
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struct cfg_entry {
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enum ks2_serdes_clock clk;
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enum ks2_serdes_rate rate;
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struct serdes_cfg cmu[SERDES_CMU_CFG_NUM];
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struct serdes_cfg comlane[SERDES_COMLANE_CFG_NUM];
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struct serdes_cfg lane[SERDES_LANE_CFG_NUM];
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};
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/* SERDES PHY lane enable configuration value, indexed by PHY interface */
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static u32 serdes_cfg_lane_enable[] = {
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0xf000f0c0, /* SGMII */
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0xf0e9f038, /* PCSR */
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};
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/* SERDES PHY PLL enable configuration value, indexed by PHY interface */
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static u32 serdes_cfg_pll_enable[] = {
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0xe0000000, /* SGMII */
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0xee000000, /* PCSR */
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};
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/**
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* Array to hold all possible serdes configurations.
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* Combination for 5 clock settings and 6 baud rates.
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*/
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static struct cfg_entry cfgs[] = {
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{
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.clk = SERDES_CLOCK_156P25M,
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.rate = SERDES_RATE_5G,
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.cmu = {
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{0x0000, 0x00800000, 0xffff0000},
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{0x0014, 0x00008282, 0x0000ffff},
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{0x0060, 0x00142438, 0x00ffffff},
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{0x0064, 0x00c3c700, 0x00ffff00},
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{0x0078, 0x0000c000, 0x0000ff00}
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},
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.comlane = {
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{0x0a00, 0x00000800, 0x0000ff00},
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{0x0a08, 0x38a20000, 0xffff0000},
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{0x0a30, 0x008a8a00, 0x00ffff00},
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{0x0a84, 0x00000600, 0x0000ff00},
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{0x0a94, 0x10000000, 0xff000000},
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{0x0aa0, 0x81000000, 0xff000000},
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{0x0abc, 0xff000000, 0xff000000},
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{0x0ac0, 0x0000008b, 0x000000ff},
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{0x0b08, 0x583f0000, 0xffff0000},
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{0x0b0c, 0x0000004e, 0x000000ff}
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},
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.lane = {
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{0x0004, 0x38000080, 0xff0000ff},
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{0x0008, 0x00000000, 0x000000ff},
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{0x000c, 0x02000000, 0xff000000},
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{0x0010, 0x1b000000, 0xff000000},
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{0x0014, 0x00006fb8, 0x0000ffff},
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{0x0018, 0x758000e4, 0xffff00ff},
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{0x00ac, 0x00004400, 0x0000ff00},
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{0x002c, 0x00100800, 0x00ffff00},
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{0x0080, 0x00820082, 0x00ff00ff},
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{0x0084, 0x1d0f0385, 0xffffffff}
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},
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},
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};
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static inline void ks2_serdes_rmw(u32 addr, u32 value, u32 mask)
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{
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writel(((readl(addr) & (~mask)) | (value & mask)), addr);
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}
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static void ks2_serdes_cfg_setup(u32 base, struct serdes_cfg *cfg, u32 size)
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{
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u32 i;
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for (i = 0; i < size; i++)
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ks2_serdes_rmw(base + cfg[i].ofs, cfg[i].val, cfg[i].mask);
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}
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static void ks2_serdes_lane_config(u32 base, struct serdes_cfg *cfg_lane,
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u32 size, u32 lane)
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{
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u32 i;
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for (i = 0; i < size; i++)
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ks2_serdes_rmw(base + cfg_lane[i].ofs + SERDES_LANE_REGS(lane),
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cfg_lane[i].val, cfg_lane[i].mask);
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}
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static int ks2_serdes_init_cfg(u32 base, struct cfg_entry *cfg, u32 num_lanes)
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{
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u32 i;
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ks2_serdes_cfg_setup(base, cfg->cmu, SERDES_CMU_CFG_NUM);
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ks2_serdes_cfg_setup(base, cfg->comlane, SERDES_COMLANE_CFG_NUM);
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for (i = 0; i < num_lanes; i++)
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ks2_serdes_lane_config(base, cfg->lane, SERDES_LANE_CFG_NUM, i);
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return 0;
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}
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static void ks2_serdes_cmu_comlane_enable(u32 base, struct ks2_serdes *serdes)
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{
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/* Bring SerDes out of Reset */
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ks2_serdes_rmw(base + SERDES_CMU_REG_010(0), 0x0, SERDES_RESET);
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if (serdes->intf == SERDES_PHY_PCSR)
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ks2_serdes_rmw(base + SERDES_CMU_REG_010(1), 0x0, SERDES_RESET);
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/* Enable CMU and COMLANE */
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ks2_serdes_rmw(base + SERDES_CMU_REG_000(0), 0x03, 0x000000ff);
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if (serdes->intf == SERDES_PHY_PCSR)
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ks2_serdes_rmw(base + SERDES_CMU_REG_000(1), 0x03, 0x000000ff);
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ks2_serdes_rmw(base + SERDES_COMLANE_REG_000, 0x5f, 0x000000ff);
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}
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static void ks2_serdes_pll_enable(u32 base, struct ks2_serdes *serdes)
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{
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writel(serdes_cfg_pll_enable[serdes->intf],
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base + SERDES_PLL_CTL_REG);
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}
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static void ks2_serdes_lane_reset(u32 base, u32 reset, u32 lane)
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{
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if (reset)
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ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane),
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0x1, SERDES_LANE_RESET);
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else
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ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane),
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0x0, SERDES_LANE_RESET);
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}
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static void ks2_serdes_lane_enable(u32 base,
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struct ks2_serdes *serdes, u32 lane)
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{
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/* Bring lane out of reset */
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ks2_serdes_lane_reset(base, 0, lane);
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writel(SERDES_LANE_EN_VAL(serdes_cfg_lane_enable, serdes->intf,
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serdes->rate_mode),
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base + SERDES_LANE_CTL_STATUS_REG(lane));
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/* Set NES bit if Loopback Enabled */
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if (serdes->loopback)
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ks2_serdes_rmw(base + SERDES_LANE_REG_000(lane),
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0x1, SERDES_LANE_LOOPBACK);
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}
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int ks2_serdes_init(u32 base, struct ks2_serdes *serdes, u32 num_lanes)
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{
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int i;
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int ret = 0;
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for (i = 0; i < ARRAY_SIZE(cfgs); i++)
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if (serdes->clk == cfgs[i].clk && serdes->rate == cfgs[i].rate)
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break;
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if (i >= ARRAY_SIZE(cfgs)) {
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puts("Cannot find keystone SerDes configuration");
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return -EINVAL;
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}
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ks2_serdes_init_cfg(base, &cfgs[i], num_lanes);
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ks2_serdes_cmu_comlane_enable(base, serdes);
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for (i = 0; i < num_lanes; i++)
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ks2_serdes_lane_enable(base, serdes, i);
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ks2_serdes_pll_enable(base, serdes);
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return ret;
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}
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