mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
129adf5bf4
Rework the driver to probe the MMC controller from Device Tree and make it mandatory. There is no longer support for probing from the ancient qts-generated header files. This patch now also removes previous temporary workaround. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com>
131 lines
3.2 KiB
C
131 lines
3.2 KiB
C
/*
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* (C) Copyright 2013 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <malloc.h>
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#include <fdtdec.h>
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#include <libfdt.h>
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#include <dwmmc.h>
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#include <errno.h>
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#include <asm/arch/dwmmc.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/arch/system_manager.h>
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static const struct socfpga_clock_manager *clock_manager_base =
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(void *)SOCFPGA_CLKMGR_ADDRESS;
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static const struct socfpga_system_manager *system_manager_base =
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(void *)SOCFPGA_SYSMGR_ADDRESS;
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static void socfpga_dwmci_clksel(struct dwmci_host *host)
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{
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unsigned int drvsel;
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unsigned int smplsel;
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/* Disable SDMMC clock. */
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clrbits_le32(&clock_manager_base->per_pll.en,
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CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
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/* Configures drv_sel and smpl_sel */
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drvsel = CONFIG_SOCFPGA_DWMMC_DRVSEL;
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smplsel = CONFIG_SOCFPGA_DWMMC_SMPSEL;
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debug("%s: drvsel %d smplsel %d\n", __func__, drvsel, smplsel);
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writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel),
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&system_manager_base->sdmmcgrp_ctrl);
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debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
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readl(&system_manager_base->sdmmcgrp_ctrl));
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/* Enable SDMMC clock */
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setbits_le32(&clock_manager_base->per_pll.en,
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CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
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}
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static int socfpga_dwmci_of_probe(const void *blob, int node, const int idx)
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{
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/* FIXME: probe from DT eventually too/ */
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const unsigned long clk = cm_get_mmc_controller_clk_hz();
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struct dwmci_host *host;
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fdt_addr_t reg_base;
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int bus_width, fifo_depth;
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if (clk == 0) {
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printf("DWMMC%d: MMC clock is zero!", idx);
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return -EINVAL;
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}
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/* Get the register address from the device node */
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reg_base = fdtdec_get_addr(blob, node, "reg");
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if (!reg_base) {
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printf("DWMMC%d: Can't get base address\n", idx);
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return -EINVAL;
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}
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/* Get the bus width from the device node */
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bus_width = fdtdec_get_int(blob, node, "bus-width", 0);
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if (bus_width <= 0) {
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printf("DWMMC%d: Can't get bus-width\n", idx);
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return -EINVAL;
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}
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fifo_depth = fdtdec_get_int(blob, node, "fifo-depth", 0);
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if (fifo_depth < 0) {
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printf("DWMMC%d: Can't get FIFO depth\n", idx);
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return -EINVAL;
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}
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/* Allocate the host */
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host = calloc(1, sizeof(*host));
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if (!host)
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return -ENOMEM;
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host->name = "SOCFPGA DWMMC";
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host->ioaddr = (void *)reg_base;
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host->buswidth = bus_width;
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host->clksel = socfpga_dwmci_clksel;
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host->dev_index = idx;
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/* Fixed clock divide by 4 which due to the SDMMC wrapper */
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host->bus_hz = clk;
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host->fifoth_val = MSIZE(0x2) |
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RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2);
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return add_dwmci(host, host->bus_hz, 400000);
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}
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static int socfpga_dwmci_process_node(const void *blob, int nodes[],
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int count)
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{
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int i, node, ret;
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for (i = 0; i < count; i++) {
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node = nodes[i];
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if (node <= 0)
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continue;
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ret = socfpga_dwmci_of_probe(blob, node, i);
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if (ret) {
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printf("%s: failed to decode dev %d\n", __func__, i);
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return ret;
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}
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}
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return 0;
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}
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int socfpga_dwmmc_init(const void *blob)
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{
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int nodes[2]; /* Max. two controllers. */
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int ret, count;
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count = fdtdec_find_aliases_for_id(blob, "mmc",
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COMPAT_ALTERA_SOCFPGA_DWMMC,
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nodes, ARRAY_SIZE(nodes));
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ret = socfpga_dwmci_process_node(blob, nodes, count);
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return ret;
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}
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