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https://github.com/brain-hackers/u-boot-brain
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587c3f8ebe
The problem is that timeout bits in WCR register were leaved unchanged. So previously set timeout value was applied and therefore 'reset' command takes any value up to two minutes, depending on previous watchdog settings, instead of minimal 0.5 seconds. Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
20 lines
383 B
C
20 lines
383 B
C
/*
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* (C) Copyright 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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struct watchdog_regs {
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u16 wcr; /* Control */
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u16 wsr; /* Service */
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u16 wrsr; /* Reset Status */
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};
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#define WCR_WDZST 0x01
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#define WCR_WDBG 0x02
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#define WCR_WDE 0x04
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#define WCR_WDT 0x08
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#define WCR_SRS 0x10
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#define SET_WCR_WT(x) (x << 8)
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#define WCR_WT_MSK SET_WCR_WT(0xFF)
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