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https://github.com/brain-hackers/u-boot-brain
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f0b5f23f32
The low four bits of the SYSCTL register are reserved on the USDHC controller on i.MX6 and i.MX7 processors, but are used for clocking operations on earlier models. Guard against their usage by hiding the bit mask macros on those processors. These bits are used to prevent glitches when changing clocks on i.MX35 et al. Use the RSTA bit instead for i.MX6 and i.MX7. >From the i.MX6DQ RM: To prevent possible glitch on the card clock, clear the FRC_SDCLK_ON bit when changing clock divisor value(SDCLKFS or DVS in System Control Register) or setting RSTA bit. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Hector Palacios <hector.palacios@digi.com>
222 lines
6.4 KiB
C
222 lines
6.4 KiB
C
/*
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* FSL SD/MMC Defines
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*-------------------------------------------------------------------
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*
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* Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSL_ESDHC_H__
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#define __FSL_ESDHC_H__
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#include <asm/errno.h>
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#include <asm/byteorder.h>
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/* needed for the mmc_cfg definition */
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#include <mmc.h>
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#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
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#include "../board/freescale/common/qixis.h"
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#endif
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/* FSL eSDHC-specific constants */
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#define SYSCTL 0x0002e02c
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#define SYSCTL_INITA 0x08000000
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#define SYSCTL_TIMEOUT_MASK 0x000f0000
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#define SYSCTL_CLOCK_MASK 0x0000fff0
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#if !defined(CONFIG_FSL_USDHC)
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#define SYSCTL_CKEN 0x00000008
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#define SYSCTL_PEREN 0x00000004
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#define SYSCTL_HCKEN 0x00000002
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#define SYSCTL_IPGEN 0x00000001
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#endif
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#define SYSCTL_RSTA 0x01000000
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#define SYSCTL_RSTC 0x02000000
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#define SYSCTL_RSTD 0x04000000
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#define IRQSTAT 0x0002e030
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#define IRQSTAT_DMAE (0x10000000)
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#define IRQSTAT_AC12E (0x01000000)
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#define IRQSTAT_DEBE (0x00400000)
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#define IRQSTAT_DCE (0x00200000)
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#define IRQSTAT_DTOE (0x00100000)
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#define IRQSTAT_CIE (0x00080000)
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#define IRQSTAT_CEBE (0x00040000)
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#define IRQSTAT_CCE (0x00020000)
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#define IRQSTAT_CTOE (0x00010000)
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#define IRQSTAT_CINT (0x00000100)
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#define IRQSTAT_CRM (0x00000080)
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#define IRQSTAT_CINS (0x00000040)
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#define IRQSTAT_BRR (0x00000020)
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#define IRQSTAT_BWR (0x00000010)
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#define IRQSTAT_DINT (0x00000008)
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#define IRQSTAT_BGE (0x00000004)
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#define IRQSTAT_TC (0x00000002)
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#define IRQSTAT_CC (0x00000001)
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#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
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#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
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IRQSTAT_DMAE)
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#define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT)
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#define IRQSTATEN 0x0002e034
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#define IRQSTATEN_DMAE (0x10000000)
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#define IRQSTATEN_AC12E (0x01000000)
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#define IRQSTATEN_DEBE (0x00400000)
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#define IRQSTATEN_DCE (0x00200000)
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#define IRQSTATEN_DTOE (0x00100000)
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#define IRQSTATEN_CIE (0x00080000)
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#define IRQSTATEN_CEBE (0x00040000)
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#define IRQSTATEN_CCE (0x00020000)
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#define IRQSTATEN_CTOE (0x00010000)
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#define IRQSTATEN_CINT (0x00000100)
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#define IRQSTATEN_CRM (0x00000080)
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#define IRQSTATEN_CINS (0x00000040)
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#define IRQSTATEN_BRR (0x00000020)
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#define IRQSTATEN_BWR (0x00000010)
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#define IRQSTATEN_DINT (0x00000008)
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#define IRQSTATEN_BGE (0x00000004)
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#define IRQSTATEN_TC (0x00000002)
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#define IRQSTATEN_CC (0x00000001)
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#define ESDHCCTL 0x0002e40c
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#define ESDHCCTL_PCS (0x00080000)
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#define PRSSTAT 0x0002e024
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#define PRSSTAT_DAT0 (0x01000000)
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#define PRSSTAT_CLSL (0x00800000)
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#define PRSSTAT_WPSPL (0x00080000)
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#define PRSSTAT_CDPL (0x00040000)
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#define PRSSTAT_CINS (0x00010000)
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#define PRSSTAT_BREN (0x00000800)
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#define PRSSTAT_BWEN (0x00000400)
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#define PRSSTAT_SDSTB (0X00000008)
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#define PRSSTAT_DLA (0x00000004)
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#define PRSSTAT_CICHB (0x00000002)
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#define PRSSTAT_CIDHB (0x00000001)
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#define PROCTL 0x0002e028
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#define PROCTL_INIT 0x00000020
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#define PROCTL_DTW_4 0x00000002
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#define PROCTL_DTW_8 0x00000004
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#define CMDARG 0x0002e008
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#define XFERTYP 0x0002e00c
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#define XFERTYP_CMD(x) ((x & 0x3f) << 24)
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#define XFERTYP_CMDTYP_NORMAL 0x0
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#define XFERTYP_CMDTYP_SUSPEND 0x00400000
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#define XFERTYP_CMDTYP_RESUME 0x00800000
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#define XFERTYP_CMDTYP_ABORT 0x00c00000
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#define XFERTYP_DPSEL 0x00200000
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#define XFERTYP_CICEN 0x00100000
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#define XFERTYP_CCCEN 0x00080000
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#define XFERTYP_RSPTYP_NONE 0
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#define XFERTYP_RSPTYP_136 0x00010000
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#define XFERTYP_RSPTYP_48 0x00020000
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#define XFERTYP_RSPTYP_48_BUSY 0x00030000
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#define XFERTYP_MSBSEL 0x00000020
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#define XFERTYP_DTDSEL 0x00000010
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#define XFERTYP_DDREN 0x00000008
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#define XFERTYP_AC12EN 0x00000004
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#define XFERTYP_BCEN 0x00000002
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#define XFERTYP_DMAEN 0x00000001
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#define CINS_TIMEOUT 1000
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#define PIO_TIMEOUT 100000
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#define DSADDR 0x2e004
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#define CMDRSP0 0x2e010
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#define CMDRSP1 0x2e014
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#define CMDRSP2 0x2e018
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#define CMDRSP3 0x2e01c
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#define DATPORT 0x2e020
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#define WML 0x2e044
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#define WML_WRITE 0x00010000
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#ifdef CONFIG_FSL_SDHC_V2_3
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#define WML_RD_WML_MAX 0x80
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#define WML_WR_WML_MAX 0x80
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#define WML_RD_WML_MAX_VAL 0x0
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#define WML_WR_WML_MAX_VAL 0x0
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#define WML_RD_WML_MASK 0x7f
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#define WML_WR_WML_MASK 0x7f0000
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#else
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#define WML_RD_WML_MAX 0x10
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#define WML_WR_WML_MAX 0x80
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#define WML_RD_WML_MAX_VAL 0x10
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#define WML_WR_WML_MAX_VAL 0x80
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#define WML_RD_WML_MASK 0xff
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#define WML_WR_WML_MASK 0xff0000
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#endif
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#define BLKATTR 0x2e004
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#define BLKATTR_CNT(x) ((x & 0xffff) << 16)
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#define BLKATTR_SIZE(x) (x & 0x1fff)
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#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */
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#define ESDHC_HOSTCAPBLT_VS18 0x04000000
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#define ESDHC_HOSTCAPBLT_VS30 0x02000000
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#define ESDHC_HOSTCAPBLT_VS33 0x01000000
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#define ESDHC_HOSTCAPBLT_SRS 0x00800000
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#define ESDHC_HOSTCAPBLT_DMAS 0x00400000
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#define ESDHC_HOSTCAPBLT_HSS 0x00200000
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#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
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struct fsl_esdhc_cfg {
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#ifdef CONFIG_FSL_LAYERSCAPE
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u64 esdhc_base;
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#else
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u32 esdhc_base;
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#endif
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u32 sdhc_clk;
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u8 max_bus_width;
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struct mmc_config cfg;
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};
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/* Select the correct accessors depending on endianess */
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#if defined CONFIG_SYS_FSL_ESDHC_LE
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#define esdhc_read32 in_le32
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#define esdhc_write32 out_le32
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#define esdhc_clrsetbits32 clrsetbits_le32
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#define esdhc_clrbits32 clrbits_le32
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#define esdhc_setbits32 setbits_le32
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#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
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#define esdhc_read32 in_be32
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#define esdhc_write32 out_be32
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#define esdhc_clrsetbits32 clrsetbits_be32
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#define esdhc_clrbits32 clrbits_be32
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#define esdhc_setbits32 setbits_be32
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#elif __BYTE_ORDER == __LITTLE_ENDIAN
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#define esdhc_read32 in_le32
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#define esdhc_write32 out_le32
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#define esdhc_clrsetbits32 clrsetbits_le32
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#define esdhc_clrbits32 clrbits_le32
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#define esdhc_setbits32 setbits_le32
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#elif __BYTE_ORDER == __BIG_ENDIAN
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#define esdhc_read32 in_be32
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#define esdhc_write32 out_be32
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#define esdhc_clrsetbits32 clrsetbits_be32
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#define esdhc_clrbits32 clrbits_be32
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#define esdhc_setbits32 setbits_be32
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#else
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#error "Endianess is not defined: please fix to continue"
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#endif
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#ifdef CONFIG_FSL_ESDHC
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int fsl_esdhc_mmc_init(bd_t *bis);
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int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
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void fdt_fixup_esdhc(void *blob, bd_t *bd);
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#else
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static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
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static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
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#endif /* CONFIG_FSL_ESDHC */
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void __noreturn mmc_boot(void);
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void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
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#endif /* __FSL_ESDHC_H__ */
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