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https://github.com/brain-hackers/u-boot-brain
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The Debug Server driver is responsible for loading the Debug server FW on the Service Processor (Cortex-A5 core) on LS2085A like SoCs and then polling for the successful initialization of the same. TOP MEM HIDE is adjusted to ensure the space required by Debug Server FW is accounted for. MC uses the DDR area which is calculated as: MC DDR region start = Top of DDR - area reserved by Debug Server FW Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
33 lines
729 B
C
33 lines
729 B
C
/*
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* Copyright (C) 2014 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSL_DBG_SERVER_H__
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#define __FSL_DBG_SERVER_H__
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#include <asm/io.h>
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#include <common.h>
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/*
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* Define Debug Server firmware version information
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*/
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/* Major version number: incremented on API compatibility changes */
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#define DEBUG_SERVER_VER_MAJOR 0
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/* Minor version number: incremented on API additions (backward
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* compatible); reset when major version is incremented.
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*/
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#define DEBUG_SERVER_VER_MINOR 1
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#define DEBUG_SERVER_INIT_STATUS (1 << 0)
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#define DEBUG_SERVER_INIT_STATUS_MASK (0x00000001)
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int debug_server_init(void);
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unsigned long debug_server_get_dram_block_size(void);
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#endif /* __FSL_DBG_SERVER_H__ */
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