mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
1238d0143a
So far U-Boot was hard coding a (surely sufficient) memory size of 512 MB, even though all machines out there have at least 4GB of DRAM. Since U-Boot uses its memory knowledge to populate the EFI memory map, we are missing out here, at best losing everything beyond 4GB on Midway boxes (which typically come with 8GB of DRAM). Since the management processor populated the DT memory node already with the detected DRAM size and configuration, we use that to populate U-Boot's memory bank information, which is the base for the UEFI memory map. This finally allows us to get rid of the NR_DRAM_BANKS=0 hack, that we had in place to avoid U-Boot messing up the DT memory node before loading the kernel. Also, to cover the whole of memory, we need to enable PHYS_64BIT. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
152 lines
2.9 KiB
C
152 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2010-2011 Calxeda, Inc.
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*/
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#include <common.h>
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#include <ahci.h>
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#include <cpu_func.h>
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#include <env.h>
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#include <fdt_support.h>
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#include <fdtdec.h>
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#include <init.h>
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#include <net.h>
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#include <scsi.h>
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#include <asm/global_data.h>
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#include <linux/sizes.h>
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#include <asm/io.h>
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#define HB_AHCI_BASE 0xffe08000
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#define HB_SCU_A9_PWR_STATUS 0xfff10008
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#define HB_SREG_A9_PWR_REQ 0xfff3cf00
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#define HB_SREG_A9_BOOT_SRC_STAT 0xfff3cf04
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#define HB_SREG_A9_PWRDOM_STAT 0xfff3cf20
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#define HB_SREG_A15_PWR_CTRL 0xfff3c200
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#define HB_PWR_SUSPEND 0
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#define HB_PWR_SOFT_RESET 1
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#define HB_PWR_HARD_RESET 2
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#define HB_PWR_SHUTDOWN 3
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#define PWRDOM_STAT_SATA 0x80000000
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#define PWRDOM_STAT_PCI 0x40000000
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#define PWRDOM_STAT_EMMC 0x20000000
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#define HB_SCU_A9_PWR_NORMAL 0
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#define HB_SCU_A9_PWR_DORMANT 2
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#define HB_SCU_A9_PWR_OFF 3
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DECLARE_GLOBAL_DATA_PTR;
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void cphy_disable_overrides(void);
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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icache_enable();
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return 0;
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}
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#ifdef CONFIG_SCSI_AHCI_PLAT
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void scsi_init(void)
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{
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u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
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cphy_disable_overrides();
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if (reg & PWRDOM_STAT_SATA) {
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ahci_init((void __iomem *)HB_AHCI_BASE);
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scsi_scan(true);
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}
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}
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#endif
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#ifdef CONFIG_MISC_INIT_R
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int misc_init_r(void)
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{
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char envbuffer[16];
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u32 boot_choice;
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boot_choice = readl(HB_SREG_A9_BOOT_SRC_STAT) & 0xff;
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sprintf(envbuffer, "bootcmd%d", boot_choice);
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if (env_get(envbuffer)) {
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sprintf(envbuffer, "run bootcmd%d", boot_choice);
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env_set("bootcmd", envbuffer);
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} else
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env_set("bootcmd", "");
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return 0;
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}
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#endif
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int dram_init(void)
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{
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return fdtdec_setup_mem_size_base();
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}
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int dram_init_banksize(void)
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{
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return fdtdec_setup_memory_banksize();
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *fdt, struct bd_info *bd)
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{
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static const char disabled[] = "disabled";
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u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
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if (!(reg & PWRDOM_STAT_SATA))
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do_fixup_by_compat(fdt, "calxeda,hb-ahci", "status",
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disabled, sizeof(disabled), 1);
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if (!(reg & PWRDOM_STAT_EMMC))
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do_fixup_by_compat(fdt, "calxeda,hb-sdhci", "status",
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disabled, sizeof(disabled), 1);
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return 0;
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}
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#endif
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void *board_fdt_blob_setup(void)
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{
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/*
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* The ECME management processor loads the DTB from NOR flash
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* into DRAM (at 4KB), where it gets patched to contain the
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* detected memory size.
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*/
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return (void *)0x1000;
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}
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static int is_highbank(void)
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{
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uint32_t midr;
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asm volatile ("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr));
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return (midr & 0xfff0) == 0xc090;
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}
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void reset_cpu(void)
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{
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writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ);
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if (is_highbank())
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writeb(HB_SCU_A9_PWR_OFF, HB_SCU_A9_PWR_STATUS);
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else
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writel(0x1, HB_SREG_A15_PWR_CTRL);
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wfi();
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}
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/*
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* turn off the override before transferring control to Linux, since Linux
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* may not support spread spectrum.
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*/
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void arch_preboot_os(void)
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{
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cphy_disable_overrides();
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}
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