mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 22:26:16 +09:00
4a69366967
Converting GPIO to DM requires to do changes in reset subsystem
that's why support for Microblaze soft reset via sysreset and GPIO
sysreset support was added.
These two patches enables enabling GPIO DM.
Microblaze soft reset is bind at last reset method.
GPIO reset is handled via sysreset with adding this fragment to DT.
gpio-restart {
compatible = "gpio-restart";
gpios = <&reset_gpio 0 0 0>;
/* 3rd cell ACTIVE_HIGH = 0, ACTIVE_LOW = 1 */
};
hard-reset-gpio property is not documented and also handled.
Conversion is required.
Unfortunately do_reset is required for SPL that's why use only soft
microblaze reset for now.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
115 lines
2.4 KiB
C
115 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2007-2018 Michal Simek
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*
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* Michal SIMEK <monstr@monstr.eu>
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*/
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/*
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* This is a board specific file. It's OK to include board specific
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* header files
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*/
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#include <common.h>
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#include <config.h>
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#include <dm.h>
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#include <dm/lists.h>
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#include <fdtdec.h>
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#include <asm/processor.h>
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#include <asm/microblaze_intc.h>
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#include <asm/asm.h>
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#include <asm/gpio.h>
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#include <dm/uclass.h>
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#include <wdt.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
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static struct udevice *watchdog_dev;
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#endif /* !CONFIG_SPL_BUILD && CONFIG_WDT */
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ulong ram_base;
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = ram_base;
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gd->bd->bi_dram[0].size = get_effective_memsize();
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return 0;
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}
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int dram_init(void)
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{
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int node;
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fdt_addr_t addr;
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fdt_size_t size;
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const void *blob = gd->fdt_blob;
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node = fdt_node_offset_by_prop_value(blob, -1, "device_type",
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"memory", 7);
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if (node == -FDT_ERR_NOTFOUND) {
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debug("DRAM: Can't get memory node\n");
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return 1;
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}
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addr = fdtdec_get_addr_size(blob, node, "reg", &size);
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if (addr == FDT_ADDR_T_NONE || size == 0) {
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debug("DRAM: Can't get base address or size\n");
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return 1;
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}
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ram_base = addr;
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gd->ram_top = addr; /* In setup_dest_addr() is done +ram_size */
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gd->ram_size = size;
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return 0;
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};
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#ifdef CONFIG_WDT
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/* Called by macro WATCHDOG_RESET */
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void watchdog_reset(void)
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{
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#if !defined(CONFIG_SPL_BUILD)
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ulong now;
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static ulong next_reset;
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if (!watchdog_dev)
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return;
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now = timer_get_us();
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/* Do not reset the watchdog too often */
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if (now > next_reset) {
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wdt_reset(watchdog_dev);
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next_reset = now + 1000;
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}
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#endif /* !CONFIG_SPL_BUILD */
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}
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#endif /* CONFIG_WDT */
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int board_late_init(void)
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{
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#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
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watchdog_dev = NULL;
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if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) {
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debug("Watchdog: Not found by seq!\n");
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if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
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puts("Watchdog: Not found!\n");
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return 0;
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}
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}
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wdt_start(watchdog_dev, 0, 0);
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puts("Watchdog: Started\n");
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#endif /* !CONFIG_SPL_BUILD && CONFIG_WDT */
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#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SYSRESET_MICROBLAZE)
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int ret;
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ret = device_bind_driver(gd->dm_root, "mb_soft_reset",
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"reset_soft", NULL);
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if (ret)
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printf("Warning: No reset driver: ret=%d\n", ret);
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#endif
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return 0;
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}
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