mirror of
https://github.com/brain-hackers/u-boot-brain
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a509161a21
The L2 cache is used as a temporary SRAM on SPL. Now the secondary CPUs store the necessary code for jumping to Linux on their L1 I-caches. So, the L2 cache can be disabled much earlier, at the very entry of U-Boot proper (lowlevel_init). This makes the boot sequence clearer. Also, as the L1 cache has been disabled by the start.S, enable_caches() does not need to do it again. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
18 lines
336 B
ArmAsm
18 lines
336 B
ArmAsm
/*
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* Copyright (C) 2015 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/linkage.h>
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#include <mach/ssc-regs.h>
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ENTRY(lowlevel_init)
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ldr r1, = SSCC
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ldr r0, [r1]
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bic r0, r0, #SSCC_ON @ L2 disable
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str r0, [r1]
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mov pc, lr
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ENDPROC(lowlevel_init)
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