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https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
019df879a9
The DDR SDRAM initialization code has not been mainlined yet, but U-Boot proper should work. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
73 lines
1.4 KiB
C
73 lines
1.4 KiB
C
/*
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* Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <mach/init.h>
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#include <mach/micro-support-card.h>
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#include <mach/soc_info.h>
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int board_early_init_f(void)
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{
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led_puts("U0");
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switch (uniphier_get_soc_type()) {
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3)
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case SOC_UNIPHIER_PH1_SLD3:
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ph1_sld3_pin_init();
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led_puts("U1");
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ph1_ld4_clk_init();
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break;
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD4)
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case SOC_UNIPHIER_PH1_LD4:
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ph1_ld4_pin_init();
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led_puts("U1");
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ph1_ld4_clk_init();
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break;
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO4)
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case SOC_UNIPHIER_PH1_PRO4:
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ph1_pro4_pin_init();
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led_puts("U1");
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ph1_pro4_clk_init();
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break;
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD8)
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case SOC_UNIPHIER_PH1_SLD8:
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ph1_sld8_pin_init();
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led_puts("U1");
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ph1_ld4_clk_init();
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break;
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_PRO5)
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case SOC_UNIPHIER_PH1_PRO5:
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ph1_pro5_pin_init();
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led_puts("U1");
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ph1_pro5_clk_init();
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break;
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PROXSTREAM2)
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case SOC_UNIPHIER_PROXSTREAM2:
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proxstream2_pin_init();
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led_puts("U1");
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proxstream2_clk_init();
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break;
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER_PH1_LD6B)
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case SOC_UNIPHIER_PH1_LD6B:
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ph1_ld6b_pin_init();
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led_puts("U1");
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proxstream2_clk_init();
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break;
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#endif
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default:
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break;
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}
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led_puts("U2");
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return 0;
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}
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