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https://github.com/brain-hackers/u-boot-brain
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11b0102218
Due to new TI boards being added to U-Boot, the hardware.h is getting very messy. The warning being fixed is due to the EMIF addresses being redefined. The long term solution(after 2009.11) to this is to have SOC specific header files. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
210 lines
7.1 KiB
C
210 lines
7.1 KiB
C
/*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* Based on:
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*
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* -------------------------------------------------------------------------
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*
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* linux/include/asm-arm/arch-davinci/hardware.h
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*
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* Copyright (C) 2006 Texas Instruments.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#include <config.h>
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#include <asm/sizes.h>
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#define REG(addr) (*(volatile unsigned int *)(addr))
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#define REG_P(addr) ((volatile unsigned int *)(addr))
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typedef volatile unsigned int dv_reg;
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typedef volatile unsigned int * dv_reg_p;
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/*
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* Base register addresses
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*
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* NOTE: some of these DM6446-specific addresses DO NOT WORK
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* on other DaVinci chips. Double check them before you try
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* using the addresses ... or PSC module identifiers, etc.
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*/
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#define DAVINCI_DMA_3PCC_BASE (0x01c00000)
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#define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
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#define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
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#define DAVINCI_UART0_BASE (0x01c20000)
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#define DAVINCI_UART1_BASE (0x01c20400)
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#define DAVINCI_I2C_BASE (0x01c21000)
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#define DAVINCI_TIMER0_BASE (0x01c21400)
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#define DAVINCI_TIMER1_BASE (0x01c21800)
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#define DAVINCI_WDOG_BASE (0x01c21c00)
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#define DAVINCI_PWM0_BASE (0x01c22000)
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#define DAVINCI_PWM1_BASE (0x01c22400)
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#define DAVINCI_PWM2_BASE (0x01c22800)
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#define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000)
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#define DAVINCI_PLL_CNTRL0_BASE (0x01c40800)
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#define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00)
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#define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000)
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#define DAVINCI_ARM_INTC_BASE (0x01c48000)
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#define DAVINCI_USB_OTG_BASE (0x01c64000)
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#define DAVINCI_CFC_ATA_BASE (0x01c66000)
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#define DAVINCI_SPI_BASE (0x01c66800)
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#define DAVINCI_GPIO_BASE (0x01c67000)
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#define DAVINCI_VPSS_REGS_BASE (0x01c70000)
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#if !defined(CONFIG_SOC_DM646X)
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#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
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#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
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#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
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#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
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#endif
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#define DAVINCI_DDR_BASE (0x80000000)
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#ifdef CONFIG_SOC_DM644X
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#define DAVINCI_UART2_BASE 0x01c20800
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#define DAVINCI_UHPI_BASE 0x01c67800
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#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01c80000
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#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01c81000
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#define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01c82000
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#define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01c84000
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#define DAVINCI_IMCOP_BASE 0x01cc0000
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#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e00000
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#define DAVINCI_VLYNQ_BASE 0x01e01000
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#define DAVINCI_ASP_BASE 0x01e02000
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#define DAVINCI_MMC_SD_BASE 0x01e10000
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#define DAVINCI_MS_BASE 0x01e20000
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#define DAVINCI_VLYNQ_REMOTE_BASE 0x0c000000
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#elif defined(CONFIG_SOC_DM355)
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#define DAVINCI_MMC_SD1_BASE 0x01e00000
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#define DAVINCI_ASP0_BASE 0x01e02000
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#define DAVINCI_ASP1_BASE 0x01e04000
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#define DAVINCI_UART2_BASE 0x01e06000
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#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000
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#define DAVINCI_MMC_SD0_BASE 0x01e11000
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#elif defined(CONFIG_SOC_DM365)
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#define DAVINCI_MMC_SD1_BASE 0x01d00000
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#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000
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#define DAVINCI_MMC_SD0_BASE 0x01d11000
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#elif defined(CONFIG_SOC_DM646X)
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#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000
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#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
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#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x44000000
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#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x46000000
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#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
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#endif
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/* Power and Sleep Controller (PSC) Domains */
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#define DAVINCI_GPSC_ARMDOMAIN 0
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#define DAVINCI_GPSC_DSPDOMAIN 1
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#define DAVINCI_LPSC_VPSSMSTR 0
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#define DAVINCI_LPSC_VPSSSLV 1
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#define DAVINCI_LPSC_TPCC 2
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#define DAVINCI_LPSC_TPTC0 3
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#define DAVINCI_LPSC_TPTC1 4
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#define DAVINCI_LPSC_EMAC 5
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#define DAVINCI_LPSC_EMAC_WRAPPER 6
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#define DAVINCI_LPSC_MDIO 7
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#define DAVINCI_LPSC_IEEE1394 8
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#define DAVINCI_LPSC_USB 9
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#define DAVINCI_LPSC_ATA 10
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#define DAVINCI_LPSC_VLYNQ 11
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#define DAVINCI_LPSC_UHPI 12
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#define DAVINCI_LPSC_DDR_EMIF 13
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#define DAVINCI_LPSC_AEMIF 14
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#define DAVINCI_LPSC_MMC_SD 15
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#define DAVINCI_LPSC_MEMSTICK 16
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#define DAVINCI_LPSC_McBSP 17
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#define DAVINCI_LPSC_I2C 18
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#define DAVINCI_LPSC_UART0 19
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#define DAVINCI_LPSC_UART1 20
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#define DAVINCI_LPSC_UART2 21
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#define DAVINCI_LPSC_SPI 22
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#define DAVINCI_LPSC_PWM0 23
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#define DAVINCI_LPSC_PWM1 24
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#define DAVINCI_LPSC_PWM2 25
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#define DAVINCI_LPSC_GPIO 26
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#define DAVINCI_LPSC_TIMER0 27
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#define DAVINCI_LPSC_TIMER1 28
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#define DAVINCI_LPSC_TIMER2 29
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#define DAVINCI_LPSC_SYSTEM_SUBSYS 30
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#define DAVINCI_LPSC_ARM 31
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#define DAVINCI_LPSC_SCR2 32
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#define DAVINCI_LPSC_SCR3 33
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#define DAVINCI_LPSC_SCR4 34
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#define DAVINCI_LPSC_CROSSBAR 35
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#define DAVINCI_LPSC_CFG27 36
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#define DAVINCI_LPSC_CFG3 37
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#define DAVINCI_LPSC_CFG5 38
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#define DAVINCI_LPSC_GEM 39
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#define DAVINCI_LPSC_IMCOP 40
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#define DAVINCI_DM646X_LPSC_EMAC 14
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#define DAVINCI_DM646X_LPSC_UART0 26
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#define DAVINCI_DM646X_LPSC_I2C 31
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void lpsc_on(unsigned int id);
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void dsp_on(void);
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void davinci_enable_uart0(void);
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void davinci_enable_emac(void);
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void davinci_enable_i2c(void);
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void davinci_errata_workarounds(void);
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/* Some PSC defines */
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#define PSC_CHP_SHRTSW (0x01c40038)
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#define PSC_GBLCTL (0x01c41010)
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#define PSC_EPCPR (0x01c41070)
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#define PSC_EPCCR (0x01c41078)
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#define PSC_PTCMD (0x01c41120)
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#define PSC_PTSTAT (0x01c41128)
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#define PSC_PDSTAT (0x01c41200)
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#define PSC_PDSTAT1 (0x01c41204)
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#define PSC_PDCTL (0x01c41300)
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#define PSC_PDCTL1 (0x01c41304)
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#define PSC_MDCTL_BASE (0x01c41a00)
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#define PSC_MDSTAT_BASE (0x01c41800)
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#define VDD3P3V_PWDN (0x01c40048)
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#define UART0_PWREMU_MGMT (0x01c20030)
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#define PSC_SILVER_BULLET (0x01c41a20)
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/* Miscellania... */
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#define VBPR (0x20000020)
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/* NOTE: system control modules are *highly* chip-specific, both
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* as to register content (e.g. for muxing) and which registers exist.
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*/
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#define PINMUX0 0x01c40000
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#define PINMUX1 0x01c40004
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#define PINMUX2 0x01c40008
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#define PINMUX3 0x01c4000c
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#define PINMUX4 0x01c40010
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#endif /* __ASM_ARCH_HARDWARE_H */
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