mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 00:18:51 +09:00
![Jeroen Hofstee](/assets/img/avatar_default.png)
lcd_base is available as gd->fb_base as well, there is no need to keep a seperate copy. For completeness the ack of Bo Shen is for the atmel part. Cc: Alessandro Rubini <rubini@unipv.it> Cc: Anatolij Gustschin <agust@denx.de> Cc: Bo Shen <voice.shen@atmel.com> Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Simon Glass <sjg@chromium.org> Cc: Stelian Pop <stelian@popies.net> Cc: Tom Warren <twarren@nvidia.com> Acked-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl> [agust: also fix cm_t35 board while rebasing] Signed-off-by: Anatolij Gustschin <agust@denx.de>
316 lines
8.7 KiB
C
316 lines
8.7 KiB
C
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <lcd.h>
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#include <asm/system.h>
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#include <asm/gpio.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/funcmux.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch/pwm.h>
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#include <asm/arch/display.h>
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#include <asm/arch-tegra/timer.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* These are the stages we go throuh in enabling the LCD */
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enum stage_t {
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STAGE_START,
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STAGE_PANEL_VDD,
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STAGE_LVDS,
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STAGE_BACKLIGHT_VDD,
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STAGE_PWM,
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STAGE_BACKLIGHT_EN,
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STAGE_DONE,
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};
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static enum stage_t stage; /* Current stage we are at */
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static unsigned long timer_next; /* Time we can move onto next stage */
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/* Our LCD config, set up in handle_stage() */
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static struct fdt_panel_config config;
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struct fdt_disp_config *disp_config; /* Display controller config */
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enum {
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/* Maximum LCD size we support */
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LCD_MAX_WIDTH = 1366,
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LCD_MAX_HEIGHT = 768,
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LCD_MAX_LOG2_BPP = 4, /* 2^4 = 16 bpp */
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};
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vidinfo_t panel_info = {
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/* Insert a value here so that we don't end up in the BSS */
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.vl_col = -1,
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};
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#ifndef CONFIG_OF_CONTROL
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#error "You must enable CONFIG_OF_CONTROL to get Tegra LCD support"
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#endif
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static void update_panel_size(struct fdt_disp_config *config)
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{
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panel_info.vl_col = config->width;
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panel_info.vl_row = config->height;
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panel_info.vl_bpix = config->log2_bpp;
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}
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/*
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* Main init function called by lcd driver.
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* Inits and then prints test pattern if required.
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*/
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void lcd_ctrl_init(void *lcdbase)
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{
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int type = DCACHE_OFF;
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int size;
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assert(disp_config);
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/* Make sure that we can acommodate the selected LCD */
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assert(disp_config->width <= LCD_MAX_WIDTH);
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assert(disp_config->height <= LCD_MAX_HEIGHT);
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assert(disp_config->log2_bpp <= LCD_MAX_LOG2_BPP);
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if (disp_config->width <= LCD_MAX_WIDTH
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&& disp_config->height <= LCD_MAX_HEIGHT
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&& disp_config->log2_bpp <= LCD_MAX_LOG2_BPP)
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update_panel_size(disp_config);
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size = lcd_get_size(&lcd_line_length);
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/* Set up the LCD caching as requested */
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if (config.cache_type & FDT_LCD_CACHE_WRITE_THROUGH)
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type = DCACHE_WRITETHROUGH;
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else if (config.cache_type & FDT_LCD_CACHE_WRITE_BACK)
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type = DCACHE_WRITEBACK;
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mmu_set_region_dcache_behaviour(disp_config->frame_buffer, size, type);
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/* Enable flushing after LCD writes if requested */
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lcd_set_flush_dcache(config.cache_type & FDT_LCD_CACHE_FLUSH);
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debug("LCD frame buffer at %08X\n", disp_config->frame_buffer);
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}
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ulong calc_fbsize(void)
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{
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return (panel_info.vl_col * panel_info.vl_row *
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NBITS(panel_info.vl_bpix)) / 8;
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}
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void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
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{
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}
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void tegra_lcd_early_init(const void *blob)
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{
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/*
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* Go with the maximum size for now. We will fix this up after
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* relocation. These values are only used for memory alocation.
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*/
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panel_info.vl_col = LCD_MAX_WIDTH;
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panel_info.vl_row = LCD_MAX_HEIGHT;
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panel_info.vl_bpix = LCD_MAX_LOG2_BPP;
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}
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/**
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* Decode the panel information from the fdt.
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*
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* @param blob fdt blob
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* @param config structure to store fdt config into
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* @return 0 if ok, -ve on error
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*/
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static int fdt_decode_lcd(const void *blob, struct fdt_panel_config *config)
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{
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int display_node;
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disp_config = tegra_display_get_config();
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if (!disp_config) {
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debug("%s: Display controller is not configured\n", __func__);
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return -1;
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}
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display_node = disp_config->panel_node;
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if (display_node < 0) {
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debug("%s: No panel configuration available\n", __func__);
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return -1;
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}
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config->pwm_channel = pwm_request(blob, display_node, "nvidia,pwm");
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if (config->pwm_channel < 0) {
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debug("%s: Unable to request PWM channel\n", __func__);
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return -1;
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}
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config->cache_type = fdtdec_get_int(blob, display_node,
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"nvidia,cache-type",
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FDT_LCD_CACHE_WRITE_BACK_FLUSH);
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/* These GPIOs are all optional */
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fdtdec_decode_gpio(blob, display_node, "nvidia,backlight-enable-gpios",
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&config->backlight_en);
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fdtdec_decode_gpio(blob, display_node, "nvidia,lvds-shutdown-gpios",
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&config->lvds_shutdown);
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fdtdec_decode_gpio(blob, display_node, "nvidia,backlight-vdd-gpios",
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&config->backlight_vdd);
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fdtdec_decode_gpio(blob, display_node, "nvidia,panel-vdd-gpios",
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&config->panel_vdd);
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return fdtdec_get_int_array(blob, display_node, "nvidia,panel-timings",
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config->panel_timings, FDT_LCD_TIMINGS);
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}
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/**
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* Handle the next stage of device init
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*/
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static int handle_stage(const void *blob)
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{
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debug("%s: stage %d\n", __func__, stage);
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/* do the things for this stage */
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switch (stage) {
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case STAGE_START:
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/* Initialize the Tegra display controller */
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if (tegra_display_probe(gd->fdt_blob, (void *)gd->fb_base)) {
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printf("%s: Failed to probe display driver\n",
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__func__);
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return -1;
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}
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/* get panel details */
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if (fdt_decode_lcd(blob, &config)) {
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printf("No valid LCD information in device tree\n");
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return -1;
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}
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/*
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* It is possible that the FDT has requested that the LCD be
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* disabled. We currently don't support this. It would require
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* changes to U-Boot LCD subsystem to have LCD support
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* compiled in but not used. An easier option might be to
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* still have a frame buffer, but leave the backlight off and
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* remove all mention of lcd in the stdout environment
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* variable.
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*/
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funcmux_select(PERIPH_ID_DISP1, FUNCMUX_DEFAULT);
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fdtdec_setup_gpio(&config.panel_vdd);
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fdtdec_setup_gpio(&config.lvds_shutdown);
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fdtdec_setup_gpio(&config.backlight_vdd);
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fdtdec_setup_gpio(&config.backlight_en);
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/*
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* TODO: If fdt includes output flag we can omit this code
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* since fdtdec_setup_gpio will do it for us.
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*/
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if (fdt_gpio_isvalid(&config.panel_vdd))
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gpio_direction_output(config.panel_vdd.gpio, 0);
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if (fdt_gpio_isvalid(&config.lvds_shutdown))
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gpio_direction_output(config.lvds_shutdown.gpio, 0);
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if (fdt_gpio_isvalid(&config.backlight_vdd))
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gpio_direction_output(config.backlight_vdd.gpio, 0);
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if (fdt_gpio_isvalid(&config.backlight_en))
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gpio_direction_output(config.backlight_en.gpio, 0);
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break;
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case STAGE_PANEL_VDD:
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if (fdt_gpio_isvalid(&config.panel_vdd))
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gpio_direction_output(config.panel_vdd.gpio, 1);
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break;
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case STAGE_LVDS:
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if (fdt_gpio_isvalid(&config.lvds_shutdown))
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gpio_set_value(config.lvds_shutdown.gpio, 1);
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break;
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case STAGE_BACKLIGHT_VDD:
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if (fdt_gpio_isvalid(&config.backlight_vdd))
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gpio_set_value(config.backlight_vdd.gpio, 1);
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break;
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case STAGE_PWM:
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/* Enable PWM at 15/16 high, 32768 Hz with divider 1 */
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pinmux_set_func(PINGRP_GPU, PMUX_FUNC_PWM);
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pinmux_tristate_disable(PINGRP_GPU);
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pwm_enable(config.pwm_channel, 32768, 0xdf, 1);
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break;
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case STAGE_BACKLIGHT_EN:
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if (fdt_gpio_isvalid(&config.backlight_en))
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gpio_set_value(config.backlight_en.gpio, 1);
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break;
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case STAGE_DONE:
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break;
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}
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/* set up timer for next stage */
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timer_next = timer_get_us();
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if (stage < FDT_LCD_TIMINGS)
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timer_next += config.panel_timings[stage] * 1000;
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/* move to next stage */
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stage++;
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return 0;
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}
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int tegra_lcd_check_next_stage(const void *blob, int wait)
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{
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if (stage == STAGE_DONE)
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return 0;
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do {
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/* wait if we need to */
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debug("%s: stage %d\n", __func__, stage);
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if (stage != STAGE_START) {
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int delay = timer_next - timer_get_us();
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if (delay > 0) {
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if (wait)
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udelay(delay);
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else
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return 0;
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}
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}
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if (handle_stage(blob))
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return -1;
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} while (wait && stage != STAGE_DONE);
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if (stage == STAGE_DONE)
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debug("%s: LCD init complete\n", __func__);
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return 0;
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}
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void lcd_enable(void)
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{
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/*
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* Backlight and power init will be done separately in
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* tegra_lcd_check_next_stage(), which should be called in
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* board_late_init().
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*
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* U-Boot code supports only colour depth, selected at compile time.
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* The device tree setting should match this. Otherwise the display
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* will not look right, and U-Boot may crash.
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*/
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if (disp_config->log2_bpp != LCD_BPP) {
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printf("%s: Error: LCD depth configured in FDT (%d = %dbpp)"
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" must match setting of LCD_BPP (%d)\n", __func__,
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disp_config->log2_bpp, disp_config->bpp, LCD_BPP);
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}
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}
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