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![Nikita Kiryanov](/assets/img/avatar_default.png)
Add generic mmc write protection functionality. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
688 lines
16 KiB
C
688 lines
16 KiB
C
/*
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* Copyright (C) 2011 Andes Technology Corporation
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <mmc.h>
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#include <asm/io.h>
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#include <faraday/ftsdc010.h>
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/*
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* supported mmc hosts
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* setting the number CONFIG_FTSDC010_NUMBER in your configuration file.
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*/
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static struct mmc ftsdc010_dev[CONFIG_FTSDC010_NUMBER];
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static struct mmc_host ftsdc010_host[CONFIG_FTSDC010_NUMBER];
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static struct ftsdc010_mmc *ftsdc010_get_base_mmc(int dev_index)
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{
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return (struct ftsdc010_mmc *)CONFIG_FTSDC010_BASE + dev_index;
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}
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#ifdef DEBUG
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static void ftsdc010_dump_reg(struct mmc_host *host)
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{
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debug("cmd: %08x\n", readl(&host->reg->cmd));
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debug("argu: %08x\n", readl(&host->reg->argu));
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debug("rsp0: %08x\n", readl(&host->reg->rsp0));
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debug("rsp1: %08x\n", readl(&host->reg->rsp1));
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debug("rsp2: %08x\n", readl(&host->reg->rsp2));
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debug("rsp3: %08x\n", readl(&host->reg->rsp3));
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debug("rsp_cmd: %08x\n", readl(&host->reg->rsp_cmd));
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debug("dcr: %08x\n", readl(&host->reg->dcr));
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debug("dtr: %08x\n", readl(&host->reg->dtr));
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debug("dlr: %08x\n", readl(&host->reg->dlr));
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debug("status: %08x\n", readl(&host->reg->status));
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debug("clr: %08x\n", readl(&host->reg->clr));
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debug("int_mask: %08x\n", readl(&host->reg->int_mask));
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debug("pcr: %08x\n", readl(&host->reg->pcr));
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debug("ccr: %08x\n", readl(&host->reg->ccr));
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debug("bwr: %08x\n", readl(&host->reg->bwr));
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debug("dwr: %08x\n", readl(&host->reg->dwr));
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debug("feature: %08x\n", readl(&host->reg->feature));
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debug("rev: %08x\n", readl(&host->reg->rev));
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}
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#endif
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static unsigned int enable_imask(struct ftsdc010_mmc *reg, unsigned int imask)
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{
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unsigned int newmask;
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newmask = readl(®->int_mask);
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newmask |= imask;
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writel(newmask, ®->int_mask);
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return newmask;
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}
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static void ftsdc010_pio_read(struct mmc_host *host, char *buf, unsigned int size)
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{
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unsigned int fifo;
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unsigned int fifo_words;
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unsigned int *ptr;
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unsigned int status;
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unsigned int retry = 0;
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/* get_data_buffer */
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ptr = (unsigned int *)buf;
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while (size) {
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status = readl(&host->reg->status);
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debug("%s: size: %08x\n", __func__, size);
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if (status & FTSDC010_STATUS_FIFO_ORUN) {
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debug("%s: FIFO OVERRUN: sta: %08x\n",
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__func__, status);
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fifo = host->fifo_len > size ?
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size : host->fifo_len;
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size -= fifo;
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fifo_words = fifo >> 2;
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while (fifo_words--)
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*ptr++ = readl(&host->reg->dwr);
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/*
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* for adding some delays for SD card to put
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* data into FIFO again
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*/
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udelay(4*FTSDC010_DELAY_UNIT);
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#ifdef CONFIG_FTSDC010_SDIO
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/* sdio allow non-power-of-2 blksz */
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if (fifo & 3) {
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unsigned int n = fifo & 3;
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unsigned int data = readl(&host->reg->dwr);
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unsigned char *p = (unsigned char *)ptr;
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while (n--) {
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*p++ = data;
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data >>= 8;
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}
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}
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#endif
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} else {
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udelay(1);
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if (++retry >= FTSDC010_PIO_RETRY) {
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debug("%s: PIO_RETRY timeout\n", __func__);
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return;
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}
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}
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}
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}
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static void ftsdc010_pio_write(struct mmc_host *host, const char *buf,
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unsigned int size)
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{
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unsigned int fifo;
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unsigned int *ptr;
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unsigned int status;
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unsigned int retry = 0;
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/* get data buffer */
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ptr = (unsigned int *)buf;
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while (size) {
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status = readl(&host->reg->status);
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if (status & FTSDC010_STATUS_FIFO_URUN) {
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fifo = host->fifo_len > size ?
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size : host->fifo_len;
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size -= fifo;
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fifo = (fifo + 3) >> 2;
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while (fifo--) {
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writel(*ptr, &host->reg->dwr);
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ptr++;
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}
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} else {
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udelay(1);
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if (++retry >= FTSDC010_PIO_RETRY) {
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debug("%s: PIO_RETRY timeout\n", __func__);
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return;
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}
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}
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}
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}
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static int ftsdc010_check_rsp(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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struct mmc_host *host = mmc->priv;
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unsigned int sta, clear;
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sta = readl(&host->reg->status);
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debug("%s: sta: %08x cmd %d\n", __func__, sta, cmd->cmdidx);
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/* check RSP TIMEOUT or FAIL */
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if (sta & FTSDC010_STATUS_RSP_TIMEOUT) {
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/* RSP TIMEOUT */
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debug("%s: RSP timeout: sta: %08x\n", __func__, sta);
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clear |= FTSDC010_CLR_RSP_TIMEOUT;
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writel(clear, &host->reg->clr);
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return TIMEOUT;
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} else if (sta & FTSDC010_STATUS_RSP_CRC_FAIL) {
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/* clear response fail bit */
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debug("%s: RSP CRC FAIL: sta: %08x\n", __func__, sta);
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clear |= FTSDC010_CLR_RSP_CRC_FAIL;
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writel(clear, &host->reg->clr);
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return COMM_ERR;
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} else if (sta & FTSDC010_STATUS_RSP_CRC_OK) {
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/* clear response CRC OK bit */
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clear |= FTSDC010_CLR_RSP_CRC_OK;
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}
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writel(clear, &host->reg->clr);
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return 0;
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}
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static int ftsdc010_check_data(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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struct mmc_host *host = mmc->priv;
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unsigned int sta, clear;
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sta = readl(&host->reg->status);
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debug("%s: sta: %08x cmd %d\n", __func__, sta, cmd->cmdidx);
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/* check DATA TIMEOUT or FAIL */
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if (data) {
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/* Transfer Complete */
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if (sta & FTSDC010_STATUS_DATA_END)
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clear |= FTSDC010_STATUS_DATA_END;
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/* Data CRC_OK */
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if (sta & FTSDC010_STATUS_DATA_CRC_OK)
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clear |= FTSDC010_STATUS_DATA_CRC_OK;
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/* DATA TIMEOUT or DATA CRC FAIL */
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if (sta & FTSDC010_STATUS_DATA_TIMEOUT) {
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/* DATA TIMEOUT */
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debug("%s: DATA TIMEOUT: sta: %08x\n", __func__, sta);
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clear |= FTSDC010_STATUS_DATA_TIMEOUT;
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writel(clear, &host->reg->clr);
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return TIMEOUT;
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} else if (sta & FTSDC010_STATUS_DATA_CRC_FAIL) {
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/* DATA CRC FAIL */
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debug("%s: DATA CRC FAIL: sta: %08x\n", __func__, sta);
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clear |= FTSDC010_STATUS_DATA_CRC_FAIL;
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writel(clear, &host->reg->clr);
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return COMM_ERR;
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}
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writel(clear, &host->reg->clr);
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}
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return 0;
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}
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static int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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struct mmc_host *host = mmc->priv;
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#ifdef CONFIG_FTSDC010_SDIO
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unsigned int scon;
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#endif
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unsigned int ccon;
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unsigned int mask, tmpmask;
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unsigned int ret;
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unsigned int sta, i;
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ret = 0;
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if (data)
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mask = FTSDC010_INT_MASK_RSP_TIMEOUT;
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else if (cmd->resp_type & MMC_RSP_PRESENT)
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mask = FTSDC010_INT_MASK_RSP_TIMEOUT;
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else
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mask = FTSDC010_INT_MASK_CMD_SEND;
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/* write argu reg */
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debug("%s: argu: %08x\n", __func__, host->reg->argu);
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writel(cmd->cmdarg, &host->reg->argu);
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/* setup commnad */
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ccon = FTSDC010_CMD_IDX(cmd->cmdidx);
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/* setup command flags */
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ccon |= FTSDC010_CMD_CMD_EN;
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/*
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* This hardware didn't support specific commands for mapping
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* MMC_RSP_BUSY and MMC_RSP_OPCODE. Hence we don't deal with it.
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*/
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if (cmd->resp_type & MMC_RSP_PRESENT) {
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ccon |= FTSDC010_CMD_NEED_RSP;
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mask |= FTSDC010_INT_MASK_RSP_CRC_OK |
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FTSDC010_INT_MASK_RSP_CRC_FAIL;
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}
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if (cmd->resp_type & MMC_RSP_136)
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ccon |= FTSDC010_CMD_LONG_RSP;
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/* In Linux driver, MMC_CMD_APP_CMD is checked in last_opcode */
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if (host->last_opcode == MMC_CMD_APP_CMD)
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ccon |= FTSDC010_CMD_APP_CMD;
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#ifdef CONFIG_FTSDC010_SDIO
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scon = readl(&host->reg->sdio_ctrl1);
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if (host->card_type == MMC_TYPE_SDIO)
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scon |= FTSDC010_SDIO_CTRL1_SDIO_ENABLE;
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else
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scon &= ~FTSDC010_SDIO_CTRL1_SDIO_ENABLE;
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writel(scon, &host->reg->sdio_ctrl1);
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#endif
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/* record last opcode for specifing the command type to hardware */
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host->last_opcode = cmd->cmdidx;
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/* write int_mask reg */
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tmpmask = readl(&host->reg->int_mask);
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tmpmask |= mask;
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writel(tmpmask, &host->reg->int_mask);
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/* write cmd reg */
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debug("%s: ccon: %08x\n", __func__, ccon);
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writel(ccon, &host->reg->cmd);
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/* check CMD_SEND */
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for (i = 0; i < FTSDC010_CMD_RETRY; i++) {
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/*
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* If we read status register too fast
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* will lead hardware error and the RSP_TIMEOUT
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* flag will be raised incorrectly.
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*/
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udelay(16*FTSDC010_DELAY_UNIT);
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sta = readl(&host->reg->status);
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/* Command Complete */
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/*
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* Note:
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* Do not clear FTSDC010_CLR_CMD_SEND flag.
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* (by writing FTSDC010_CLR_CMD_SEND bit to clear register)
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* It will make the driver becomes very slow.
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* If the operation hasn't been finished, hardware will
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* clear this bit automatically.
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* In origin, the driver will clear this flag if there is
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* no data need to be read.
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*/
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if (sta & FTSDC010_STATUS_CMD_SEND)
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break;
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}
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if (i > FTSDC010_CMD_RETRY) {
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printf("%s: send command timeout\n", __func__);
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return TIMEOUT;
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}
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/* check rsp status */
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ret = ftsdc010_check_rsp(mmc, cmd, data);
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if (ret)
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return ret;
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/* read response if we have RSP_OK */
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if (ccon & FTSDC010_CMD_LONG_RSP) {
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cmd->response[0] = readl(&host->reg->rsp3);
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cmd->response[1] = readl(&host->reg->rsp2);
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cmd->response[2] = readl(&host->reg->rsp1);
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cmd->response[3] = readl(&host->reg->rsp0);
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} else {
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cmd->response[0] = readl(&host->reg->rsp0);
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}
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/* read/write data */
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if (data && (data->flags & MMC_DATA_READ)) {
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ftsdc010_pio_read(host, data->dest,
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data->blocksize * data->blocks);
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} else if (data && (data->flags & MMC_DATA_WRITE)) {
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ftsdc010_pio_write(host, data->src,
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data->blocksize * data->blocks);
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}
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/* check data status */
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if (data) {
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ret = ftsdc010_check_data(mmc, cmd, data);
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if (ret)
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return ret;
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}
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udelay(FTSDC010_DELAY_UNIT);
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return ret;
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}
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static unsigned int cal_blksz(unsigned int blksz)
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{
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unsigned int blksztwo = 0;
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while (blksz >>= 1)
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blksztwo++;
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return blksztwo;
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}
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static int ftsdc010_setup_data(struct mmc *mmc, struct mmc_data *data)
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{
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struct mmc_host *host = mmc->priv;
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unsigned int dcon, newmask;
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/* configure data transfer paramter */
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if (!data)
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return 0;
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if (((data->blocksize - 1) & data->blocksize) != 0) {
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printf("%s: can't do non-power-of 2 sized block transfers"
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" (blksz %d)\n", __func__, data->blocksize);
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return -1;
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}
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/*
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* We cannot deal with unaligned blocks with more than
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* one block being transfered.
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*/
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if ((data->blocksize <= 2) && (data->blocks > 1)) {
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printf("%s: can't do non-word sized block transfers"
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" (blksz %d)\n", __func__, data->blocksize);
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return -1;
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}
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/* data length */
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dcon = data->blocksize * data->blocks;
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writel(dcon, &host->reg->dlr);
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/* write data control */
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dcon = cal_blksz(data->blocksize);
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/* add to IMASK register */
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newmask = (FTSDC010_STATUS_RSP_CRC_FAIL | FTSDC010_STATUS_DATA_TIMEOUT);
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/*
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* enable UNDERRUN will trigger interrupt immediatedly
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* So setup it when rsp is received successfully
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*/
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if (data->flags & MMC_DATA_WRITE) {
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dcon |= FTSDC010_DCR_DATA_WRITE;
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} else {
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dcon &= ~FTSDC010_DCR_DATA_WRITE;
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newmask |= FTSDC010_STATUS_FIFO_ORUN;
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}
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enable_imask(host->reg, newmask);
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#ifdef CONFIG_FTSDC010_SDIO
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/* always reset fifo since last transfer may fail */
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dcon |= FTSDC010_DCR_FIFO_RST;
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if (data->blocks > 1)
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dcon |= FTSDC010_SDIO_CTRL1_SDIO_BLK_MODE;
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#endif
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/* enable data transfer which will be pended until cmd is send */
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dcon |= FTSDC010_DCR_DATA_EN;
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writel(dcon, &host->reg->dcr);
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return 0;
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}
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static int ftsdc010_send_request(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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int ret;
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if (data) {
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ret = ftsdc010_setup_data(mmc, data);
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if (ret) {
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printf("%s: setup data error\n", __func__);
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return -1;
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}
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if ((data->flags & MMC_DATA_BOTH_DIR) == MMC_DATA_BOTH_DIR) {
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printf("%s: data is both direction\n", __func__);
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return -1;
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}
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}
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/* Send command */
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ret = ftsdc010_send_cmd(mmc, cmd, data);
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return ret;
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}
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static int ftsdc010_card_detect(struct mmc *mmc)
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{
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struct mmc_host *host = mmc->priv;
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unsigned int sta;
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sta = readl(&host->reg->status);
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debug("%s: card status: %08x\n", __func__, sta);
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return (sta & FTSDC010_STATUS_CARD_DETECT) ? 0 : 1;
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}
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static int ftsdc010_request(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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int ret;
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if (ftsdc010_card_detect(mmc) == 0) {
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printf("%s: no medium present\n", __func__);
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return -1;
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} else {
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ret = ftsdc010_send_request(mmc, cmd, data);
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return ret;
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}
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}
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static void ftsdc010_set_clk(struct mmc *mmc)
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{
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struct mmc_host *host = mmc->priv;
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unsigned char clk_div;
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unsigned int real_rate;
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unsigned int clock;
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debug("%s: mmc_set_clock: %x\n", __func__, mmc->clock);
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clock = readl(&host->reg->ccr);
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if (mmc->clock == 0) {
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real_rate = 0;
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clock |= FTSDC010_CCR_CLK_DIS;
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} else {
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debug("%s, mmc->clock: %08x, origin clock: %08x\n",
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__func__, mmc->clock, clock);
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for (clk_div = 0; clk_div <= 127; clk_div++) {
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real_rate = (CONFIG_SYS_CLK_FREQ / 2) /
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(2 * (clk_div + 1));
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if (real_rate <= mmc->clock)
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break;
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}
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debug("%s: computed real_rate: %x, clk_div: %x\n",
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__func__, real_rate, clk_div);
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if (clk_div > 127)
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debug("%s: no match clock rate, %x\n",
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__func__, mmc->clock);
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clock = (clock & ~FTSDC010_CCR_CLK_DIV(0x7f)) |
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FTSDC010_CCR_CLK_DIV(clk_div);
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clock &= ~FTSDC010_CCR_CLK_DIS;
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}
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debug("%s, set clock: %08x\n", __func__, clock);
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writel(clock, &host->reg->ccr);
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}
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static void ftsdc010_set_ios(struct mmc *mmc)
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{
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struct mmc_host *host = mmc->priv;
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unsigned int power;
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unsigned long val;
|
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unsigned int bus_width;
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|
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debug("%s: bus_width: %x, clock: %d\n",
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__func__, mmc->bus_width, mmc->clock);
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|
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/* set pcr: power on */
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power = readl(&host->reg->pcr);
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power |= FTSDC010_PCR_POWER_ON;
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writel(power, &host->reg->pcr);
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|
|
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if (mmc->clock)
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ftsdc010_set_clk(mmc);
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|
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/* set bwr: bus width reg */
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bus_width = readl(&host->reg->bwr);
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bus_width &= ~(FTSDC010_BWR_WIDE_8_BUS | FTSDC010_BWR_WIDE_4_BUS |
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FTSDC010_BWR_SINGLE_BUS);
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|
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if (mmc->bus_width == 8)
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bus_width |= FTSDC010_BWR_WIDE_8_BUS;
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else if (mmc->bus_width == 4)
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bus_width |= FTSDC010_BWR_WIDE_4_BUS;
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else
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bus_width |= FTSDC010_BWR_SINGLE_BUS;
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writel(bus_width, &host->reg->bwr);
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/* set fifo depth */
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val = readl(&host->reg->feature);
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host->fifo_len = FTSDC010_FEATURE_FIFO_DEPTH(val) * 4; /* 4 bytes */
|
|
|
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/* set data timeout register */
|
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val = -1;
|
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writel(val, &host->reg->dtr);
|
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}
|
|
|
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static void ftsdc010_reset(struct mmc_host *host)
|
|
{
|
|
unsigned int timeout;
|
|
unsigned int sta;
|
|
|
|
/* Do SDC_RST: Software reset for all register */
|
|
writel(FTSDC010_CMD_SDC_RST, &host->reg->cmd);
|
|
|
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host->clock = 0;
|
|
|
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/* this hardware has no reset finish flag to read */
|
|
/* wait 100ms maximum */
|
|
timeout = 100;
|
|
|
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/* hw clears the bit when it's done */
|
|
while (readl(&host->reg->dtr) != 0) {
|
|
if (timeout == 0) {
|
|
printf("%s: reset timeout error\n", __func__);
|
|
return;
|
|
}
|
|
timeout--;
|
|
udelay(10*FTSDC010_DELAY_UNIT);
|
|
}
|
|
|
|
sta = readl(&host->reg->status);
|
|
if (sta & FTSDC010_STATUS_CARD_CHANGE)
|
|
writel(FTSDC010_CLR_CARD_CHANGE, &host->reg->clr);
|
|
}
|
|
|
|
static int ftsdc010_core_init(struct mmc *mmc)
|
|
{
|
|
struct mmc_host *host = mmc->priv;
|
|
unsigned int mask;
|
|
unsigned int major, minor, revision;
|
|
|
|
/* get hardware version */
|
|
host->version = readl(&host->reg->rev);
|
|
|
|
major = FTSDC010_REV_MAJOR(host->version);
|
|
minor = FTSDC010_REV_MINOR(host->version);
|
|
revision = FTSDC010_REV_REVISION(host->version);
|
|
|
|
printf("ftsdc010 hardware ver: %d_%d_r%d\n", major, minor, revision);
|
|
|
|
/* Interrupt MASK register init - mask all */
|
|
writel(0x0, &host->reg->int_mask);
|
|
|
|
mask = FTSDC010_INT_MASK_CMD_SEND |
|
|
FTSDC010_INT_MASK_DATA_END |
|
|
FTSDC010_INT_MASK_CARD_CHANGE;
|
|
#ifdef CONFIG_FTSDC010_SDIO
|
|
mask |= FTSDC010_INT_MASK_CP_READY |
|
|
FTSDC010_INT_MASK_CP_BUF_READY |
|
|
FTSDC010_INT_MASK_PLAIN_TEXT_READY |
|
|
FTSDC010_INT_MASK_SDIO_IRPT;
|
|
#endif
|
|
|
|
writel(mask, &host->reg->int_mask);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int ftsdc010_mmc_init(int dev_index)
|
|
{
|
|
struct mmc *mmc;
|
|
struct mmc_host *host;
|
|
|
|
mmc = &ftsdc010_dev[dev_index];
|
|
|
|
sprintf(mmc->name, "FTSDC010 SD/MMC");
|
|
mmc->priv = &ftsdc010_host[dev_index];
|
|
mmc->send_cmd = ftsdc010_request;
|
|
mmc->set_ios = ftsdc010_set_ios;
|
|
mmc->init = ftsdc010_core_init;
|
|
mmc->getcd = NULL;
|
|
mmc->getwp = NULL;
|
|
|
|
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
|
|
mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
|
|
|
|
mmc->f_min = CONFIG_SYS_CLK_FREQ / 2 / (2*128);
|
|
mmc->f_max = CONFIG_SYS_CLK_FREQ / 2 / 2;
|
|
|
|
ftsdc010_host[dev_index].clock = 0;
|
|
ftsdc010_host[dev_index].reg = ftsdc010_get_base_mmc(dev_index);
|
|
mmc_register(mmc);
|
|
|
|
/* reset mmc */
|
|
host = (struct mmc_host *)mmc->priv;
|
|
ftsdc010_reset(host);
|
|
|
|
return 0;
|
|
}
|