mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
007056f495
Currently, timer driver is bound only for hart0. There is no mandatory requirement that hart0 should always come up. In fact, HiFive Unleashed SoC hart0 doesn't boot in S-mode because it only has M-mode. The timer driver should be bound for boot hart. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
118 lines
2.5 KiB
C
118 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <cpu.h>
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#include <dm.h>
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#include <errno.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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DECLARE_GLOBAL_DATA_PTR;
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static int riscv_cpu_get_desc(struct udevice *dev, char *buf, int size)
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{
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const char *isa;
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isa = dev_read_string(dev, "riscv,isa");
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if (size < (strlen(isa) + 1))
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return -ENOSPC;
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strcpy(buf, isa);
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return 0;
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}
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static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info)
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{
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const char *mmu;
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dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq);
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mmu = dev_read_string(dev, "mmu-type");
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if (!mmu)
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info->features |= BIT(CPU_FEAT_MMU);
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return 0;
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}
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static int riscv_cpu_get_count(struct udevice *dev)
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{
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ofnode node;
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int num = 0;
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ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
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const char *device_type;
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device_type = ofnode_read_string(node, "device_type");
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if (!device_type)
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continue;
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if (strcmp(device_type, "cpu") == 0)
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num++;
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}
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return num;
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}
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static int riscv_cpu_bind(struct udevice *dev)
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{
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struct cpu_platdata *plat = dev_get_parent_platdata(dev);
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struct driver *drv;
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int ret;
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/* save the hart id */
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plat->cpu_id = dev_read_addr(dev);
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/* first examine the property in current cpu node */
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ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq);
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/* if not found, then look at the parent /cpus node */
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if (ret)
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dev_read_u32(dev->parent, "timebase-frequency",
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&plat->timebase_freq);
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/*
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* Bind riscv-timer driver on boot hart.
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*
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* We only instantiate one timer device which is enough for U-Boot.
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* Pass the "timebase-frequency" value as the driver data for the
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* timer device.
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*
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* Return value is not checked since it's possible that the timer
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* driver is not included.
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*/
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if (plat->cpu_id == gd->arch.boot_hart && plat->timebase_freq) {
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drv = lists_driver_lookup_name("riscv_timer");
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if (!drv) {
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debug("Cannot find the timer driver, not included?\n");
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return 0;
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}
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device_bind_with_driver_data(dev, drv, "riscv_timer",
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plat->timebase_freq, ofnode_null(),
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NULL);
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}
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return 0;
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}
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static const struct cpu_ops riscv_cpu_ops = {
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.get_desc = riscv_cpu_get_desc,
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.get_info = riscv_cpu_get_info,
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.get_count = riscv_cpu_get_count,
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};
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static const struct udevice_id riscv_cpu_ids[] = {
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{ .compatible = "riscv" },
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{ }
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};
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U_BOOT_DRIVER(riscv_cpu) = {
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.name = "riscv_cpu",
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.id = UCLASS_CPU,
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.of_match = riscv_cpu_ids,
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.bind = riscv_cpu_bind,
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.ops = &riscv_cpu_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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