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0dd38a35f4
Some DDR related structures present in fsl_ddr_dimm_params.h, fsl_ddr_sdram.h, ddr_spd.h has various parameters with embedded acronyms capitalized that trigger the CamelCase warning in checkpatch.pl Convert those variable names to smallcase naming convention and modify all files which are using these structures with modified structures. Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
111 lines
2.9 KiB
C
111 lines
2.9 KiB
C
/*
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* Copyright 2008,2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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struct board_specific_parameters {
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u32 n_ranks;
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u32 datarate_mhz_high;
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u32 clk_adjust;
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u32 cpo;
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u32 write_data_delay;
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};
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/*
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* This table contains all valid speeds we want to override with board
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* specific parameters. datarate_mhz_high values need to be in ascending order
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* for each n_ranks group.
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*/
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const struct board_specific_parameters dimm0[] = {
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/*
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* memory controller 0
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* num| hi| clk| cpo|wrdata|2T
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* ranks| mhz|adjst| | delay|
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*/
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{4, 333, 7, 7, 3},
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{4, 549, 7, 9, 3},
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{4, 650, 7, 10, 4},
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{2, 333, 7, 7, 3},
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{2, 549, 7, 9, 3},
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{2, 650, 7, 10, 4},
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{1, 333, 7, 7, 3},
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{1, 549, 7, 9, 3},
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{1, 650, 7, 10, 4},
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{}
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};
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/*
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* The two slots have slightly different timing. The center values are good
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* for both slots. We use identical speed tables for them. In future use, if
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* DIMMs have fewer center values that require two separated tables, copy the
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* udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
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*/
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const struct board_specific_parameters *dimms[] = {
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dimm0,
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dimm0,
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};
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
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unsigned int i;
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ulong ddr_freq;
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if (ctrl_num > 1) {
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printf("Wrong parameter for controller number %d", ctrl_num);
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return;
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}
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for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
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if (pdimm[i].n_ranks)
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break;
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}
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if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */
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return;
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pbsp = dimms[ctrl_num];
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/* Get clk_adjust, cpo, write_data_delay, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(0) / 1000000;
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while (pbsp->datarate_mhz_high) {
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if (pbsp->n_ranks == pdimm[i].n_ranks) {
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if (ddr_freq <= pbsp->datarate_mhz_high) {
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popts->clk_adjust = pbsp->clk_adjust;
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popts->cpo_override = pbsp->cpo;
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popts->write_data_delay =
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pbsp->write_data_delay;
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goto found;
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}
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pbsp_highest = pbsp;
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}
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pbsp++;
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}
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if (pbsp_highest) {
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printf("Error: board specific timing not found "
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"for data rate %lu MT/s!\n"
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"Trying to use the highest speed (%u) parameters\n",
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ddr_freq, pbsp_highest->datarate_mhz_high);
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popts->clk_adjust = pbsp_highest->clk_adjust;
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popts->cpo_override = pbsp_highest->cpo;
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popts->write_data_delay = pbsp_highest->write_data_delay;
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} else {
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panic("DIMM is not supported by this board");
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}
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found:
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/* 2T timing enable */
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popts->twot_en = 1;
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}
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