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https://github.com/brain-hackers/u-boot-brain
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ab9715303d
cpsw driver supports only selection of phy mode in control module but control module has more setting like RGMII ID mode selection, RMII clock source selection. So ported to cpsw-phy-sel driver from kernel to u-boot. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
59 lines
1.6 KiB
C
59 lines
1.6 KiB
C
/*
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* CPSW Ethernet Switch Driver
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*
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _CPSW_H_
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#define _CPSW_H_
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struct cpsw_slave_data {
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u32 slave_reg_ofs;
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u32 sliver_reg_ofs;
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int phy_addr;
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int phy_if;
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int phy_of_handle;
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};
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enum {
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CPSW_CTRL_VERSION_1 = 0,
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CPSW_CTRL_VERSION_2 /* am33xx like devices */
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};
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struct cpsw_platform_data {
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u32 mdio_base;
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u32 cpsw_base;
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u32 mac_id;
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u32 gmii_sel;
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int mdio_div;
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int channels; /* number of cpdma channels (symmetric) */
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u32 cpdma_reg_ofs; /* cpdma register offset */
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int slaves; /* number of slave cpgmac ports */
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u32 ale_reg_ofs; /* address lookup engine reg offset */
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int ale_entries; /* ale table size */
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u32 host_port_reg_ofs; /* cpdma host port registers */
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u32 hw_stats_reg_ofs; /* cpsw hw stats counters */
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u32 bd_ram_ofs; /* Buffer Descriptor RAM offset */
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u32 mac_control;
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struct cpsw_slave_data *slave_data;
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void (*control)(int enabled);
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u32 host_port_num;
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u32 active_slave;
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bool rmii_clock_external;
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u8 version;
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};
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int cpsw_register(struct cpsw_platform_data *data);
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int ti_cm_get_macid(struct udevice *dev, int slave, u8 *mac_addr);
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#endif /* _CPSW_H_ */
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