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![Mark Jackson](/assets/img/avatar_default.png)
Added code to setup the extra Flash and FRAM chip selects as used on the MIMC200 board. V2 moves the init code from the common "cpu.c" file into the board specific setup file. Signed-off-by: Mark Jackson <mpfj@mimc.co.uk> Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
178 lines
4.5 KiB
C
178 lines
4.5 KiB
C
/*
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* Copyright (C) 2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/sdram.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/hmatrix.h>
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#include <asm/arch/portmux.h>
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#include <lcd.h>
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#include "../../../cpu/at32ap/hsmc3.h"
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DECLARE_GLOBAL_DATA_PTR;
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static const struct sdram_config sdram_config = {
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.data_bits = SDRAM_DATA_16BIT,
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.row_bits = 13,
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.col_bits = 9,
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.bank_bits = 2,
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.cas = 3,
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.twr = 2,
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.trc = 6,
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.trp = 2,
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.trcd = 2,
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.tras = 6,
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.txsr = 6,
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/* 15.6 us */
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.refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
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};
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int board_early_init_f(void)
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{
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/* Enable SDRAM in the EBI mux */
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hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
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/* Enable 26 address bits and NCS2 */
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portmux_enable_ebi(16, 26, PORTMUX_EBI_CS(2), PORTMUX_DRIVE_HIGH);
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portmux_enable_usart1(PORTMUX_DRIVE_MIN);
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/* de-assert "force sys reset" pin */
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portmux_select_gpio(PORTMUX_PORT_D, 1 << 15,
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PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
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/* init custom i/o */
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/* cpu type inputs */
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portmux_select_gpio(PORTMUX_PORT_E, (1 << 19) | (1 << 20) | (1 << 23),
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PORTMUX_DIR_INPUT);
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/* main board type inputs */
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portmux_select_gpio(PORTMUX_PORT_B, (1 << 19) | (1 << 29),
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PORTMUX_DIR_INPUT);
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/* DEBUG input (use weak pullup) */
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portmux_select_gpio(PORTMUX_PORT_E, 1 << 21,
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PORTMUX_DIR_INPUT | PORTMUX_PULL_UP);
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/* are we suppressing the console ? */
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if (gpio_get_value(GPIO_PIN_PE(21)) == 1)
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gd->flags |= (GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE);
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/* reset phys */
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portmux_select_gpio(PORTMUX_PORT_E, 1 << 24, PORTMUX_DIR_INPUT);
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portmux_select_gpio(PORTMUX_PORT_C, 1 << 18,
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PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
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udelay(5000);
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/* release phys reset */
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gpio_set_value(GPIO_PIN_PC(18), 0); /* PHY RESET (Release) */
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/* setup Data Flash chip select (NCS2) */
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hsmc3_writel(MODE2, 0x20121003);
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hsmc3_writel(CYCLE2, 0x000a0009);
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hsmc3_writel(PULSE2, 0x0a060806);
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hsmc3_writel(SETUP2, 0x00030102);
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/* setup FRAM chip select (NCS3) */
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hsmc3_writel(MODE3, 0x10120001);
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hsmc3_writel(CYCLE3, 0x001e001d);
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hsmc3_writel(PULSE3, 0x08040704);
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hsmc3_writel(SETUP3, 0x02050204);
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#if defined(CONFIG_MACB)
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/* init macb0 pins */
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portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
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portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
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#endif
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#if defined(CONFIG_MMC)
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portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
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#endif
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return 0;
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}
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phys_size_t initdram(int board_type)
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{
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unsigned long expected_size;
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unsigned long actual_size;
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void *sdram_base;
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sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
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expected_size = sdram_init(sdram_base, &sdram_config);
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actual_size = get_ram_size(sdram_base, expected_size);
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unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
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if (expected_size != actual_size)
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printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
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actual_size >> 20, expected_size >> 20);
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return actual_size;
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}
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int board_early_init_r(void)
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{
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gd->bd->bi_phy_id[0] = 0x01;
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gd->bd->bi_phy_id[1] = 0x03;
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return 0;
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}
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int board_postclk_init(void)
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{
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/* Use GCLK0 as 10MHz output */
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gclk_enable_output(0, PORTMUX_DRIVE_LOW);
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gclk_set_rate(0, GCLK_PARENT_OSC0, 10000000);
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return 0;
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}
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/* SPI chip select control */
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#ifdef CONFIG_ATMEL_SPI
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#include <spi.h>
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return (bus == 0) && (cs == 0);
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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}
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#endif /* CONFIG_ATMEL_SPI */
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#ifdef CONFIG_CMD_NET
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int board_eth_init(bd_t *bi)
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{
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macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
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macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]);
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return 0;
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}
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#endif
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