mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-20 08:58:52 +09:00
![Marian Balakowicz](/assets/img/avatar_default.png)
Add support for three new DDR chips that may be present on a NG INKA4x0 hardware: HYB25D512160BF-5, K4H511638C-7CB3, T46V32M16BN-6IT. Cleanup board/inka4x0/mt48lc16m16a2-75.h file. Signed-off-by: Marian Balakowicz <m8@semihalf.com>
33 lines
1.1 KiB
C
33 lines
1.1 KiB
C
/*
|
|
* Copyright (C) 2007 Semihalf
|
|
* Written by Marian Balakowicz <m8@semihalf.com>
|
|
*
|
|
* See file CREDITS for list of people who contributed to this
|
|
* project.
|
|
*
|
|
* This program is free software; you can redistribute it and/or
|
|
* modify it under the terms of the GNU General Public License as
|
|
* published by the Free Software Foundation; either version 2 of
|
|
* the License, or (at your option) any later version.
|
|
*
|
|
* This program is distributed in the hope that it will be useful,
|
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
* GNU General Public License for more details.
|
|
*
|
|
* You should have received a copy of the GNU General Public License
|
|
* along with this program; if not, write to the Free Software
|
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
* MA 02111-1307 USA
|
|
*/
|
|
|
|
#define SDRAM_DDR 1 /* is DDR */
|
|
|
|
/* Settings for XLB = 132 MHz */
|
|
#define SDRAM_MODE 0x018D0000
|
|
#define SDRAM_EMODE 0x40090000
|
|
#define SDRAM_CONTROL 0x714F0F00
|
|
#define SDRAM_CONFIG1 0x73722930
|
|
#define SDRAM_CONFIG2 0x46770000
|
|
#define SDRAM_TAPDELAY 0x10000000
|