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![Simon Glass](/assets/img/avatar_default.png)
These support the flat device tree. We want to use the dev_read_..() prefix for functions that support both flat tree and live tree. So rename the existing functions to avoid confusion. In the end we will have: 1. dev_read_addr...() - works on devices, supports flat/live tree 2. devfdt_get_addr...() - current functions, flat tree only 3. of_get_address() etc. - new functions, live tree only All drivers will be written to use 1. That function will in turn call either 2 or 3 depending on whether the flat or live tree is in use. Note this involves changing some dead code - the imx_lpi2c.c file. Signed-off-by: Simon Glass <sjg@chromium.org>
562 lines
15 KiB
C
562 lines
15 KiB
C
/*
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* Copyright (c) 2016, Google Inc
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*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, d.mueller@elsoft.ch
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <i2c.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/pinmux.h>
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#include "s3c24x0_i2c.h"
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DECLARE_GLOBAL_DATA_PTR;
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/* HSI2C-specific register description */
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/* I2C_CTL Register bits */
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#define HSI2C_FUNC_MODE_I2C (1u << 0)
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#define HSI2C_MASTER (1u << 3)
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#define HSI2C_RXCHON (1u << 6) /* Write/Send */
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#define HSI2C_TXCHON (1u << 7) /* Read/Receive */
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#define HSI2C_SW_RST (1u << 31)
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/* I2C_FIFO_CTL Register bits */
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#define HSI2C_RXFIFO_EN (1u << 0)
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#define HSI2C_TXFIFO_EN (1u << 1)
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#define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16)
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#define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4)
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/* I2C_TRAILING_CTL Register bits */
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#define HSI2C_TRAILING_COUNT (0xff)
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/* I2C_INT_EN Register bits */
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#define HSI2C_TX_UNDERRUN_EN (1u << 2)
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#define HSI2C_TX_OVERRUN_EN (1u << 3)
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#define HSI2C_RX_UNDERRUN_EN (1u << 4)
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#define HSI2C_RX_OVERRUN_EN (1u << 5)
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#define HSI2C_INT_TRAILING_EN (1u << 6)
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#define HSI2C_INT_I2C_EN (1u << 9)
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#define HSI2C_INT_ERROR_MASK (HSI2C_TX_UNDERRUN_EN |\
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HSI2C_TX_OVERRUN_EN |\
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HSI2C_RX_UNDERRUN_EN |\
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HSI2C_RX_OVERRUN_EN |\
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HSI2C_INT_TRAILING_EN)
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/* I2C_CONF Register bits */
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#define HSI2C_AUTO_MODE (1u << 31)
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#define HSI2C_10BIT_ADDR_MODE (1u << 30)
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#define HSI2C_HS_MODE (1u << 29)
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/* I2C_AUTO_CONF Register bits */
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#define HSI2C_READ_WRITE (1u << 16)
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#define HSI2C_STOP_AFTER_TRANS (1u << 17)
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#define HSI2C_MASTER_RUN (1u << 31)
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/* I2C_TIMEOUT Register bits */
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#define HSI2C_TIMEOUT_EN (1u << 31)
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/* I2C_TRANS_STATUS register bits */
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#define HSI2C_MASTER_BUSY (1u << 17)
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#define HSI2C_SLAVE_BUSY (1u << 16)
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#define HSI2C_TIMEOUT_AUTO (1u << 4)
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#define HSI2C_NO_DEV (1u << 3)
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#define HSI2C_NO_DEV_ACK (1u << 2)
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#define HSI2C_TRANS_ABORT (1u << 1)
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#define HSI2C_TRANS_SUCCESS (1u << 0)
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#define HSI2C_TRANS_ERROR_MASK (HSI2C_TIMEOUT_AUTO |\
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HSI2C_NO_DEV | HSI2C_NO_DEV_ACK |\
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HSI2C_TRANS_ABORT)
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#define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS)
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/* I2C_FIFO_STAT Register bits */
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#define HSI2C_RX_FIFO_EMPTY (1u << 24)
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#define HSI2C_RX_FIFO_FULL (1u << 23)
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#define HSI2C_TX_FIFO_EMPTY (1u << 8)
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#define HSI2C_TX_FIFO_FULL (1u << 7)
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#define HSI2C_RX_FIFO_LEVEL(x) (((x) >> 16) & 0x7f)
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#define HSI2C_TX_FIFO_LEVEL(x) ((x) & 0x7f)
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#define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)
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#define HSI2C_TIMEOUT_US 10000 /* 10 ms, finer granularity */
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/*
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* Wait for transfer completion.
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*
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* This function reads the interrupt status register waiting for the INT_I2C
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* bit to be set, which indicates copletion of a transaction.
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*
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* @param i2c: pointer to the appropriate register bank
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*
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* @return: I2C_OK in case of successful completion, I2C_NOK_TIMEOUT in case
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* the status bits do not get set in time, or an approrpiate error
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* value in case of transfer errors.
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*/
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static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c)
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{
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int i = HSI2C_TIMEOUT_US;
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while (i-- > 0) {
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u32 int_status = readl(&i2c->usi_int_stat);
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if (int_status & HSI2C_INT_I2C_EN) {
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u32 trans_status = readl(&i2c->usi_trans_status);
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/* Deassert pending interrupt. */
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writel(int_status, &i2c->usi_int_stat);
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if (trans_status & HSI2C_NO_DEV_ACK) {
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debug("%s: no ACK from device\n", __func__);
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return I2C_NACK;
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}
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if (trans_status & HSI2C_NO_DEV) {
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debug("%s: no device\n", __func__);
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return I2C_NOK;
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}
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if (trans_status & HSI2C_TRANS_ABORT) {
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debug("%s: arbitration lost\n", __func__);
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return I2C_NOK_LA;
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}
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if (trans_status & HSI2C_TIMEOUT_AUTO) {
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debug("%s: device timed out\n", __func__);
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return I2C_NOK_TOUT;
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}
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return I2C_OK;
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}
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udelay(1);
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}
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debug("%s: transaction timeout!\n", __func__);
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return I2C_NOK_TOUT;
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}
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static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus)
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{
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struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
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ulong clkin;
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unsigned int op_clk = i2c_bus->clock_frequency;
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unsigned int i = 0, utemp0 = 0, utemp1 = 0;
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unsigned int t_ftl_cycle;
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#if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5)
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clkin = get_i2c_clk();
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#else
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clkin = get_PCLK();
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#endif
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/* FPCLK / FI2C =
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* (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
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* uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
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* uTemp1 = (TSCLK_L + TSCLK_H + 2)
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* uTemp2 = TSCLK_L + TSCLK_H
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*/
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t_ftl_cycle = (readl(&hsregs->usi_conf) >> 16) & 0x7;
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utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle;
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/* CLK_DIV max is 256 */
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for (i = 0; i < 256; i++) {
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utemp1 = utemp0 / (i + 1);
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if ((utemp1 < 512) && (utemp1 > 4)) {
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i2c_bus->clk_cycle = utemp1 - 2;
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i2c_bus->clk_div = i;
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return 0;
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}
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}
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return -EINVAL;
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}
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static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus)
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{
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struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
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unsigned int t_sr_release;
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unsigned int n_clkdiv;
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unsigned int t_start_su, t_start_hd;
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unsigned int t_stop_su;
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unsigned int t_data_su, t_data_hd;
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unsigned int t_scl_l, t_scl_h;
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u32 i2c_timing_s1;
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u32 i2c_timing_s2;
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u32 i2c_timing_s3;
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u32 i2c_timing_sla;
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n_clkdiv = i2c_bus->clk_div;
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t_scl_l = i2c_bus->clk_cycle / 2;
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t_scl_h = i2c_bus->clk_cycle / 2;
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t_start_su = t_scl_l;
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t_start_hd = t_scl_l;
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t_stop_su = t_scl_l;
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t_data_su = t_scl_l / 2;
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t_data_hd = t_scl_l / 2;
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t_sr_release = i2c_bus->clk_cycle;
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i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
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i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
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i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0;
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i2c_timing_sla = t_data_hd << 0;
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writel(HSI2C_TRAILING_COUNT, &hsregs->usi_trailing_ctl);
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/* Clear to enable Timeout */
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clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0);
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/* set AUTO mode */
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writel(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf);
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/* Enable completion conditions' reporting. */
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writel(HSI2C_INT_I2C_EN, &hsregs->usi_int_en);
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/* Enable FIFOs */
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writel(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl);
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/* Currently operating in Fast speed mode. */
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writel(i2c_timing_s1, &hsregs->usi_timing_fs1);
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writel(i2c_timing_s2, &hsregs->usi_timing_fs2);
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writel(i2c_timing_s3, &hsregs->usi_timing_fs3);
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writel(i2c_timing_sla, &hsregs->usi_timing_sla);
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}
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/* SW reset for the high speed bus */
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static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus)
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{
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struct exynos5_hsi2c *i2c = i2c_bus->hsregs;
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u32 i2c_ctl;
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/* Set and clear the bit for reset */
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i2c_ctl = readl(&i2c->usi_ctl);
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i2c_ctl |= HSI2C_SW_RST;
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writel(i2c_ctl, &i2c->usi_ctl);
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i2c_ctl = readl(&i2c->usi_ctl);
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i2c_ctl &= ~HSI2C_SW_RST;
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writel(i2c_ctl, &i2c->usi_ctl);
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/* Initialize the configure registers */
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hsi2c_ch_init(i2c_bus);
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}
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/*
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* Poll the appropriate bit of the fifo status register until the interface is
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* ready to process the next byte or timeout expires.
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*
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* In addition to the FIFO status register this function also polls the
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* interrupt status register to be able to detect unexpected transaction
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* completion.
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*
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* When FIFO is ready to process the next byte, this function returns I2C_OK.
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* If in course of polling the INT_I2C assertion is detected, the function
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* returns I2C_NOK. If timeout happens before any of the above conditions is
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* met - the function returns I2C_NOK_TOUT;
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* @param i2c: pointer to the appropriate i2c register bank.
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* @param rx_transfer: set to True if the receive transaction is in progress.
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* @return: as described above.
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*/
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static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer)
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{
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u32 fifo_bit = rx_transfer ? HSI2C_RX_FIFO_EMPTY : HSI2C_TX_FIFO_FULL;
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int i = HSI2C_TIMEOUT_US;
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while (readl(&i2c->usi_fifo_stat) & fifo_bit) {
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if (readl(&i2c->usi_int_stat) & HSI2C_INT_I2C_EN) {
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/*
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* There is a chance that assertion of
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* HSI2C_INT_I2C_EN and deassertion of
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* HSI2C_RX_FIFO_EMPTY happen simultaneously. Let's
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* give FIFO status priority and check it one more
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* time before reporting interrupt. The interrupt will
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* be reported next time this function is called.
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*/
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if (rx_transfer &&
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!(readl(&i2c->usi_fifo_stat) & fifo_bit))
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break;
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return I2C_NOK;
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}
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if (!i--) {
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debug("%s: FIFO polling timeout!\n", __func__);
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return I2C_NOK_TOUT;
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}
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udelay(1);
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}
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return I2C_OK;
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}
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/*
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* Preapre hsi2c transaction, either read or write.
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*
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* Set up transfer as described in section 27.5.1.2 'I2C Channel Auto Mode' of
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* the 5420 UM.
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*
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* @param i2c: pointer to the appropriate i2c register bank.
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* @param chip: slave address on the i2c bus (with read/write bit exlcuded)
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* @param len: number of bytes expected to be sent or received
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* @param rx_transfer: set to true for receive transactions
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* @param: issue_stop: set to true if i2c stop condition should be generated
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* after this transaction.
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* @return: I2C_NOK_TOUT in case the bus remained busy for HSI2C_TIMEOUT_US,
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* I2C_OK otherwise.
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*/
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static int hsi2c_prepare_transaction(struct exynos5_hsi2c *i2c,
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u8 chip,
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u16 len,
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bool rx_transfer,
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bool issue_stop)
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{
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u32 conf;
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conf = len | HSI2C_MASTER_RUN;
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if (issue_stop)
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conf |= HSI2C_STOP_AFTER_TRANS;
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/* Clear to enable Timeout */
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writel(readl(&i2c->usi_timeout) & ~HSI2C_TIMEOUT_EN, &i2c->usi_timeout);
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/* Set slave address */
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writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr);
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if (rx_transfer) {
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/* i2c master, read transaction */
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writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
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&i2c->usi_ctl);
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/* read up to len bytes, stop after transaction is finished */
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writel(conf | HSI2C_READ_WRITE, &i2c->usi_auto_conf);
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} else {
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/* i2c master, write transaction */
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writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER),
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&i2c->usi_ctl);
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/* write up to len bytes, stop after transaction is finished */
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writel(conf, &i2c->usi_auto_conf);
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}
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/* Reset all pending interrupt status bits we care about, if any */
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writel(HSI2C_INT_I2C_EN, &i2c->usi_int_stat);
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return I2C_OK;
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}
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/*
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* Wait while i2c bus is settling down (mostly stop gets completed).
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*/
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static int hsi2c_wait_while_busy(struct exynos5_hsi2c *i2c)
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{
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int i = HSI2C_TIMEOUT_US;
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while (readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) {
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if (!i--) {
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debug("%s: bus busy\n", __func__);
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return I2C_NOK_TOUT;
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}
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udelay(1);
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}
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return I2C_OK;
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}
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static int hsi2c_write(struct exynos5_hsi2c *i2c,
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unsigned char chip,
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unsigned char addr[],
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unsigned char alen,
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unsigned char data[],
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unsigned short len,
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bool issue_stop)
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{
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int i, rv = 0;
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if (!(len + alen)) {
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/* Writes of zero length not supported in auto mode. */
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debug("%s: zero length writes not supported\n", __func__);
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return I2C_NOK;
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}
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rv = hsi2c_prepare_transaction
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(i2c, chip, len + alen, false, issue_stop);
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if (rv != I2C_OK)
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return rv;
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/* Move address, if any, and the data, if any, into the FIFO. */
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for (i = 0; i < alen; i++) {
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rv = hsi2c_poll_fifo(i2c, false);
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if (rv != I2C_OK) {
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debug("%s: address write failed\n", __func__);
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goto write_error;
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}
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writel(addr[i], &i2c->usi_txdata);
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}
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for (i = 0; i < len; i++) {
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rv = hsi2c_poll_fifo(i2c, false);
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if (rv != I2C_OK) {
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debug("%s: data write failed\n", __func__);
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goto write_error;
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}
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writel(data[i], &i2c->usi_txdata);
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}
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rv = hsi2c_wait_for_trx(i2c);
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write_error:
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if (issue_stop) {
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int tmp_ret = hsi2c_wait_while_busy(i2c);
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if (rv == I2C_OK)
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rv = tmp_ret;
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}
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writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
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return rv;
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}
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static int hsi2c_read(struct exynos5_hsi2c *i2c,
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unsigned char chip,
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unsigned char addr[],
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unsigned char alen,
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unsigned char data[],
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unsigned short len)
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{
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int i, rv, tmp_ret;
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bool drop_data = false;
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if (!len) {
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/* Reads of zero length not supported in auto mode. */
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debug("%s: zero length read adjusted\n", __func__);
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drop_data = true;
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len = 1;
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}
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|
if (alen) {
|
|
/* Internal register adress needs to be written first. */
|
|
rv = hsi2c_write(i2c, chip, addr, alen, NULL, 0, false);
|
|
if (rv != I2C_OK)
|
|
return rv;
|
|
}
|
|
|
|
rv = hsi2c_prepare_transaction(i2c, chip, len, true, true);
|
|
|
|
if (rv != I2C_OK)
|
|
return rv;
|
|
|
|
for (i = 0; i < len; i++) {
|
|
rv = hsi2c_poll_fifo(i2c, true);
|
|
if (rv != I2C_OK)
|
|
goto read_err;
|
|
if (drop_data)
|
|
continue;
|
|
data[i] = readl(&i2c->usi_rxdata);
|
|
}
|
|
|
|
rv = hsi2c_wait_for_trx(i2c);
|
|
|
|
read_err:
|
|
tmp_ret = hsi2c_wait_while_busy(i2c);
|
|
if (rv == I2C_OK)
|
|
rv = tmp_ret;
|
|
|
|
writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */
|
|
return rv;
|
|
}
|
|
|
|
static int exynos_hs_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
|
|
int nmsgs)
|
|
{
|
|
struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
|
|
struct exynos5_hsi2c *hsregs = i2c_bus->hsregs;
|
|
int ret;
|
|
|
|
for (; nmsgs > 0; nmsgs--, msg++) {
|
|
if (msg->flags & I2C_M_RD) {
|
|
ret = hsi2c_read(hsregs, msg->addr, 0, 0, msg->buf,
|
|
msg->len);
|
|
} else {
|
|
ret = hsi2c_write(hsregs, msg->addr, 0, 0, msg->buf,
|
|
msg->len, true);
|
|
}
|
|
if (ret) {
|
|
exynos5_i2c_reset(i2c_bus);
|
|
return -EREMOTEIO;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int s3c24x0_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
|
|
{
|
|
struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
|
|
|
|
i2c_bus->clock_frequency = speed;
|
|
|
|
if (hsi2c_get_clk_details(i2c_bus))
|
|
return -EFAULT;
|
|
hsi2c_ch_init(i2c_bus);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int s3c24x0_i2c_probe(struct udevice *dev, uint chip, uint chip_flags)
|
|
{
|
|
struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
|
|
uchar buf[1];
|
|
int ret;
|
|
|
|
buf[0] = 0;
|
|
|
|
/*
|
|
* What is needed is to send the chip address and verify that the
|
|
* address was <ACK>ed (i.e. there was a chip at that address which
|
|
* drove the data line low).
|
|
*/
|
|
ret = hsi2c_read(i2c_bus->hsregs, chip, 0, 0, buf, 1);
|
|
|
|
return ret != I2C_OK;
|
|
}
|
|
|
|
static int s3c_i2c_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
const void *blob = gd->fdt_blob;
|
|
struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
|
|
int node;
|
|
|
|
node = dev_of_offset(dev);
|
|
|
|
i2c_bus->hsregs = (struct exynos5_hsi2c *)devfdt_get_addr(dev);
|
|
|
|
i2c_bus->id = pinmux_decode_periph_id(blob, node);
|
|
|
|
i2c_bus->clock_frequency = fdtdec_get_int(blob, node,
|
|
"clock-frequency", 100000);
|
|
i2c_bus->node = node;
|
|
i2c_bus->bus_num = dev->seq;
|
|
|
|
exynos_pinmux_config(i2c_bus->id, PINMUX_FLAG_HS_MODE);
|
|
|
|
i2c_bus->active = true;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_i2c_ops exynos_hs_i2c_ops = {
|
|
.xfer = exynos_hs_i2c_xfer,
|
|
.probe_chip = s3c24x0_i2c_probe,
|
|
.set_bus_speed = s3c24x0_i2c_set_bus_speed,
|
|
};
|
|
|
|
static const struct udevice_id exynos_hs_i2c_ids[] = {
|
|
{ .compatible = "samsung,exynos5-hsi2c" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(hs_i2c) = {
|
|
.name = "i2c_s3c_hs",
|
|
.id = UCLASS_I2C,
|
|
.of_match = exynos_hs_i2c_ids,
|
|
.ofdata_to_platdata = s3c_i2c_ofdata_to_platdata,
|
|
.priv_auto_alloc_size = sizeof(struct s3c24x0_i2c_bus),
|
|
.ops = &exynos_hs_i2c_ops,
|
|
};
|