mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
142 lines
3.5 KiB
C
142 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <ns16550.h>
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#include <dm/platform_data/lpc32xx_hsuart.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/uart.h>
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#include <asm/arch/mux.h>
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#include <asm/io.h>
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static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
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static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
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static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;
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void lpc32xx_uart_init(unsigned int uart_id)
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{
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if (uart_id < 1 || uart_id > 7)
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return;
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/* Disable loopback mode, if it is set by S1L bootloader */
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clrbits_le32(&ctrl->loop,
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UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART));
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if (uart_id < 3 || uart_id > 6)
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return;
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/* Enable UART system clock */
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setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id));
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/* Set UART into autoclock mode */
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clrsetbits_le32(&ctrl->clkmode,
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UART_CLKMODE_MASK(uart_id),
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UART_CLKMODE_AUTO(uart_id));
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/* Bypass pre-divider of UART clock */
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writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
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&clk->u3clk + (uart_id - 3));
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}
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#if !CONFIG_IS_ENABLED(OF_CONTROL)
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static const struct ns16550_platdata lpc32xx_uart[] = {
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{ .base = UART3_BASE, .reg_shift = 2,
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.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
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{ .base = UART4_BASE, .reg_shift = 2,
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.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
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{ .base = UART5_BASE, .reg_shift = 2,
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.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
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{ .base = UART6_BASE, .reg_shift = 2,
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.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
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};
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#if defined(CONFIG_LPC32XX_HSUART)
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static const struct lpc32xx_hsuart_platdata lpc32xx_hsuart[] = {
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{ HS_UART1_BASE, },
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{ HS_UART2_BASE, },
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{ HS_UART7_BASE, },
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};
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#endif
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U_BOOT_DEVICES(lpc32xx_uarts) = {
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#if defined(CONFIG_LPC32XX_HSUART)
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{ "lpc32xx_hsuart", &lpc32xx_hsuart[0], },
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{ "lpc32xx_hsuart", &lpc32xx_hsuart[1], },
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#endif
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{ "ns16550_serial", &lpc32xx_uart[0], },
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{ "ns16550_serial", &lpc32xx_uart[1], },
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{ "ns16550_serial", &lpc32xx_uart[2], },
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{ "ns16550_serial", &lpc32xx_uart[3], },
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#if defined(CONFIG_LPC32XX_HSUART)
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{ "lpc32xx_hsuart", &lpc32xx_hsuart[2], },
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#endif
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};
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#endif
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void lpc32xx_dma_init(void)
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{
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/* Enable DMA interface */
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writel(CLK_DMA_ENABLE, &clk->dmaclk_ctrl);
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}
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void lpc32xx_mac_init(void)
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{
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/* Enable MAC interface */
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writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
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#if defined(CONFIG_RMII)
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| CLK_MAC_RMII,
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#else
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| CLK_MAC_MII,
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#endif
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&clk->macclk_ctrl);
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}
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void lpc32xx_mlc_nand_init(void)
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{
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/* Enable NAND interface */
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writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
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}
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void lpc32xx_slc_nand_init(void)
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{
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/* Enable SLC NAND interface */
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writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl);
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}
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void lpc32xx_usb_init(void)
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{
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/* Do not route the UART 5 Tx/Rx pins to the USB D+ and USB D- pins. */
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clrbits_le32(&ctrl->ctrl, UART_CTRL_UART5_USB_MODE);
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}
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void lpc32xx_i2c_init(unsigned int devnum)
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{
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/* Enable I2C interface */
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uint32_t ctrl = readl(&clk->i2cclk_ctrl);
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if (devnum == 1)
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ctrl |= CLK_I2C1_ENABLE;
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if (devnum == 2)
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ctrl |= CLK_I2C2_ENABLE;
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writel(ctrl, &clk->i2cclk_ctrl);
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}
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U_BOOT_DEVICE(lpc32xx_gpios) = {
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.name = "gpio_lpc32xx"
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};
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/* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */
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#define P_MUX_SET_SSP0 0x1600
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void lpc32xx_ssp_init(void)
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{
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/* Enable SSP0 interface */
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writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl);
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/* Mux SSP0 pins */
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writel(P_MUX_SET_SSP0, &mux->p_mux_set);
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}
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