mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
96 lines
2.4 KiB
C
96 lines
2.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Cirrus Logic EP93xx PLL support.
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*
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* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
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*/
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#include <common.h>
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#include <asm/arch/ep93xx.h>
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#include <asm/io.h>
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#include <div64.h>
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/*
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* CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
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*
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* get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
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* the specified bus in HZ.
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*/
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/*
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* return the PLL output frequency
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*
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* PLL rate = CONFIG_SYS_CLK_FREQ * (X1FBD + 1) * (X2FBD + 1)
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* / (X2IPD + 1) / 2^PS
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*/
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static ulong get_PLLCLK(uint32_t *pllreg)
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{
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uint8_t i;
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const uint32_t clkset = readl(pllreg);
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uint64_t rate = CONFIG_SYS_CLK_FREQ;
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rate *= ((clkset >> SYSCON_CLKSET_PLL_X1FBD1_SHIFT) & 0x1f) + 1;
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rate *= ((clkset >> SYSCON_CLKSET_PLL_X2FBD2_SHIFT) & 0x3f) + 1;
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do_div(rate, (clkset & 0x1f) + 1); /* X2IPD */
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for (i = 0; i < ((clkset >> SYSCON_CLKSET_PLL_PS_SHIFT) & 3); i++)
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rate >>= 1;
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return (ulong)rate;
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}
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/* return FCLK frequency */
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ulong get_FCLK(void)
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{
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const uint8_t fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
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struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
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const uint32_t clkset1 = readl(&syscon->clkset1);
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const uint8_t fclk_div =
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fclk_divisors[(clkset1 >> SYSCON_CLKSET1_FCLK_DIV_SHIFT) & 7];
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const ulong fclk_rate = get_PLLCLK(&syscon->clkset1) / fclk_div;
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return fclk_rate;
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}
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/* return HCLK frequency */
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ulong get_HCLK(void)
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{
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const uint8_t hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
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struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
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const uint32_t clkset1 = readl(&syscon->clkset1);
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const uint8_t hclk_div =
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hclk_divisors[(clkset1 >> SYSCON_CLKSET1_HCLK_DIV_SHIFT) & 7];
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const ulong hclk_rate = get_PLLCLK(&syscon->clkset1) / hclk_div;
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return hclk_rate;
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}
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/* return PCLK frequency */
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ulong get_PCLK(void)
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{
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const uint8_t pclk_divisors[] = { 1, 2, 4, 8 };
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struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
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const uint32_t clkset1 = readl(&syscon->clkset1);
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const uint8_t pclk_div =
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pclk_divisors[(clkset1 >> SYSCON_CLKSET1_PCLK_DIV_SHIFT) & 3];
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const ulong pclk_rate = get_HCLK() / pclk_div;
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return pclk_rate;
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}
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/* return UCLK frequency */
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ulong get_UCLK(void)
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{
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struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
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ulong uclk_rate;
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const uint32_t value = readl(&syscon->pwrcnt);
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if (value & SYSCON_PWRCNT_UART_BAUD)
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uclk_rate = CONFIG_SYS_CLK_FREQ;
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else
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uclk_rate = CONFIG_SYS_CLK_FREQ / 2;
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return uclk_rate;
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}
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