mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
458 lines
10 KiB
ArmAsm
458 lines
10 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Low-level initialization for EP93xx
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*
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* Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
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* Copyright (C) 2013
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* Sergey Kostanabev <sergey.kostanbaev <at> fairwaves.ru>
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*
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* Copyright (C) 2006 Dominic Rath <Dominic.Rath@gmx.de>
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* Copyright (C) 2006 Cirrus Logic Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*/
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#include <config.h>
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#include <asm/arch-ep93xx/ep93xx.h>
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/*
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/* Configure the SDRAM based on the supplied settings.
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*
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* Input: r0 - SDRAM DEVCFG register
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* r2 - configuration for SDRAM chips
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* Output: none
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* Modifies: r3, r4
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*/
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ep93xx_sdram_config:
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/* Program the SDRAM device configuration register. */
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ldr r3, =SDRAM_BASE
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#ifdef CONFIG_EDB93XX_SDCS0
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str r0, [r3, #SDRAM_OFF_DEVCFG0]
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#endif
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#ifdef CONFIG_EDB93XX_SDCS1
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str r0, [r3, #SDRAM_OFF_DEVCFG1]
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#endif
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#ifdef CONFIG_EDB93XX_SDCS2
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str r0, [r3, #SDRAM_OFF_DEVCFG2]
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#endif
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#ifdef CONFIG_EDB93XX_SDCS3
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str r0, [r3, #SDRAM_OFF_DEVCFG3]
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#endif
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/* Set the Initialize and MRS bits (issue continuous NOP commands
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* (INIT & MRS set))
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*/
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ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
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EP93XX_SDRAMCTRL_GLOBALCFG_MRS | \
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EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
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str r4, [r3, #SDRAM_OFF_GLCONFIG]
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/* Delay for 200us. */
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mov r4, #0x3000
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delay1:
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subs r4, r4, #1
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bne delay1
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/* Clear the MRS bit to issue a precharge all. */
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ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
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EP93XX_SDRAMCTRL_GLOBALCFG_CKE)
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str r4, [r3, #SDRAM_OFF_GLCONFIG]
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/* Temporarily set the refresh timer to 0x10. Make it really low so
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* that refresh cycles are generated.
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*/
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ldr r4, =0x10
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str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
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/* Delay for at least 80 SDRAM clock cycles. */
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mov r4, #80
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delay2:
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subs r4, r4, #1
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bne delay2
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/* Set the refresh timer to the fastest required for any device
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* that might be used. Set 9.6 ms refresh time.
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*/
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ldr r4, =0x01e0
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str r4, [r3, #SDRAM_OFF_REFRSHTIMR]
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/* Select mode register update mode. */
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ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_CKE | \
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EP93XX_SDRAMCTRL_GLOBALCFG_MRS)
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str r4, [r3, #SDRAM_OFF_GLCONFIG]
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/* Program the mode register on the SDRAM by performing fake read */
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ldr r4, [r2]
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/* Select normal operating mode. */
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ldr r4, =EP93XX_SDRAMCTRL_GLOBALCFG_CKE
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str r4, [r3, #SDRAM_OFF_GLCONFIG]
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/* Return to the caller. */
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mov pc, lr
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/*
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* Test to see if the SDRAM has been configured in a usable mode.
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*
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* Input: r0 - Test address of SDRAM
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* Output: r0 - 0 -- Test OK, -1 -- Failed
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* Modifies: r0-r5
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*/
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ep93xx_sdram_test:
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/* Load the test patterns to be written to SDRAM. */
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ldr r1, =0xf00dface
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ldr r2, =0xdeadbeef
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ldr r3, =0x08675309
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ldr r4, =0xdeafc0ed
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/* Store the test patterns to SDRAM. */
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stmia r0, {r1-r4}
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/* Load the test patterns from SDRAM one at a time and compare them
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* to the actual pattern.
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*/
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ldr r5, [r0]
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cmp r5, r1
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ldreq r5, [r0, #0x0004]
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cmpeq r5, r2
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ldreq r5, [r0, #0x0008]
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cmpeq r5, r3
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ldreq r5, [r0, #0x000c]
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cmpeq r5, r4
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/* Return -1 if a mismatch was encountered, 0 otherwise. */
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mvnne r0, #0xffffffff
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moveq r0, #0x00000000
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/* Return to the caller. */
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mov pc, lr
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/*
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* Determine the size of the SDRAM. Use data=address for the scan.
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*
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* Input: r0 - Start SDRAM address
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* Return: r0 - Single block size
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* r1 - Valid block mask
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* r2 - Total block count
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* Modifies: r0-r5
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*/
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ep93xx_sdram_size:
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/* Store zero at offset zero. */
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str r0, [r0]
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/* Start checking for an alias at 1MB into SDRAM. */
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ldr r1, =0x00100000
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/* Store the offset at the current offset. */
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check_block_size:
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str r1, [r0, r1]
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/* Read back from zero. */
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ldr r2, [r0]
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/* Stop searching of an alias was found. */
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cmp r1, r2
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beq found_block_size
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/* Advance to the next power of two boundary. */
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mov r1, r1, lsl #1
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/* Loop back if the size has not reached 256MB. */
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cmp r1, #0x10000000
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bne check_block_size
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/* A full 256MB of memory was found, so return it now. */
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ldr r0, =0x10000000
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ldr r1, =0x00000000
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ldr r2, =0x00000001
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mov pc, lr
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/* An alias was found. See if the first block is 128MB in size. */
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found_block_size:
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cmp r1, #0x08000000
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/* The first block is 128MB, so there is no further memory. Return it
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* now.
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*/
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ldreq r0, =0x08000000
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ldreq r1, =0x00000000
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ldreq r2, =0x00000001
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moveq pc, lr
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/* Save the block size, set the block address bits to zero, and
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* initialize the block count to one.
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*/
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mov r3, r1
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ldr r4, =0x00000000
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ldr r5, =0x00000001
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/* Look for additional blocks of memory by searching for non-aliases. */
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find_blocks:
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/* Store zero back to address zero. It may be overwritten. */
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str r0, [r0]
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/* Advance to the next power of two boundary. */
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mov r1, r1, lsl #1
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/* Store the offset at the current offset. */
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str r1, [r0, r1]
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/* Read back from zero. */
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ldr r2, [r0]
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/* See if a non-alias was found. */
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cmp r1, r2
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/* If a non-alias was found, then or in the block address bit and
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* multiply the block count by two (since there are two unique
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* blocks, one with this bit zero and one with it one).
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*/
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orrne r4, r4, r1
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movne r5, r5, lsl #1
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/* Continue searching if there are more address bits to check. */
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cmp r1, #0x08000000
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bne find_blocks
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/* Return the block size, address mask, and count. */
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mov r0, r3
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mov r1, r4
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mov r2, r5
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/* Return to the caller. */
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mov pc, lr
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.globl lowlevel_init
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lowlevel_init:
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mov r6, lr
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/* Make sure caches are off and invalidated. */
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ldr r0, =0x00000000
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mcr p15, 0, r0, c1, c0, 0
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nop
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nop
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nop
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nop
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nop
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/* Turn off the green LED and turn on the red LED. If the red LED
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* is left on for too long, the external reset circuit described
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* by application note AN258 will cause the system to reset.
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*/
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ldr r1, =EP93XX_LED_DATA
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ldr r0, [r1]
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bic r0, r0, #EP93XX_LED_GREEN_ON
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orr r0, r0, #EP93XX_LED_RED_ON
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str r0, [r1]
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/* Undo the silly static memory controller programming performed
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* by the boot rom.
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*/
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ldr r0, =SMC_BASE
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/* Set WST1 and WST2 to 31 HCLK cycles (slowest access) */
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ldr r1, =0x0000fbe0
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/* Reset EP93XX_OFF_SMCBCR0 */
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ldr r2, [r0]
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orr r2, r2, r1
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str r2, [r0]
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ldr r2, [r0, #EP93XX_OFF_SMCBCR1]
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orr r2, r2, r1
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str r2, [r0, #EP93XX_OFF_SMCBCR1]
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ldr r2, [r0, #EP93XX_OFF_SMCBCR2]
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orr r2, r2, r1
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str r2, [r0, #EP93XX_OFF_SMCBCR2]
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ldr r2, [r0, #EP93XX_OFF_SMCBCR3]
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orr r2, r2, r1
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str r2, [r0, #EP93XX_OFF_SMCBCR3]
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ldr r2, [r0, #EP93XX_OFF_SMCBCR6]
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orr r2, r2, r1
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str r2, [r0, #EP93XX_OFF_SMCBCR6]
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ldr r2, [r0, #EP93XX_OFF_SMCBCR7]
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orr r2, r2, r1
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str r2, [r0, #EP93XX_OFF_SMCBCR7]
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/* Set the PLL1 and processor clock. */
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ldr r0, =SYSCON_BASE
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#ifdef CONFIG_EDB9301
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/* 332MHz, giving a 166MHz processor clock. */
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ldr r1, = 0x02b49907
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#else
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#ifdef CONFIG_EDB93XX_INDUSTRIAL
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/* 384MHz, giving a 196MHz processor clock. */
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ldr r1, =0x02a4bb38
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#else
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/* 400MHz, giving a 200MHz processor clock. */
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ldr r1, =0x02a4e39e
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#endif
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#endif
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str r1, [r0, #SYSCON_OFF_CLKSET1]
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nop
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nop
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nop
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nop
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nop
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/* Need to make sure that SDRAM is configured correctly before
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* coping the code into it.
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*/
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#ifdef CONFIG_EDB93XX_SDCS0
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mov r11, #SDRAM_DEVCFG0_BASE
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#endif
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#ifdef CONFIG_EDB93XX_SDCS1
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mov r11, #SDRAM_DEVCFG1_BASE
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#endif
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#ifdef CONFIG_EDB93XX_SDCS2
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mov r11, #SDRAM_DEVCFG2_BASE
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#endif
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#ifdef CONFIG_EDB93XX_SDCS3
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ldr r0, =SYSCON_BASE
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ldr r0, [r0, #SYSCON_OFF_SYSCFG]
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ands r0, r0, #SYSCON_SYSCFG_LASDO
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moveq r11, #SDRAM_DEVCFG3_ASD0_BASE
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movne r11, #SDRAM_DEVCFG3_ASD1_BASE
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#endif
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/* See Table 13-5 in EP93xx datasheet for more info about DRAM
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* register mapping */
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/* Try a 32-bit wide configuration of SDRAM. */
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ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
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EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
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EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
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EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2)
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/* Set burst count: 4 and CAS: 2
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* Burst mode [A11:A10]; CAS [A16:A14]
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*/
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orr r2, r11, #0x00008800
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bl ep93xx_sdram_config
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/* Test the SDRAM. */
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mov r0, r11
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bl ep93xx_sdram_test
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cmp r0, #0x00000000
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beq ep93xx_sdram_done
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/* Try a 16-bit wide configuration of SDRAM. */
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ldr r0, =(EP93XX_SDRAMCTRL_DEVCFG_BANKCOUNT | \
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EP93XX_SDRAMCTRL_DEVCFG_SROMLL | \
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EP93XX_SDRAMCTRL_DEVCFG_CASLAT_2 | \
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EP93XX_SDRAMCTRL_DEVCFG_RASTOCAS_2 | \
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EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH)
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/* Set burst count: 8, CAS: 2, sequential burst
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* Accoring to Table 13-3 for 16bit operations mapping must be shifted.
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* Burst mode [A10:A9]; CAS [A15:A13]
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*/
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orr r2, r11, #0x00004600
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bl ep93xx_sdram_config
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/* Test the SDRAM. */
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mov r0, r11
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bl ep93xx_sdram_test
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cmp r0, #0x00000000
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beq ep93xx_sdram_done
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/* Turn off the red LED. */
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ldr r0, =EP93XX_LED_DATA
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ldr r1, [r0]
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bic r1, r1, #EP93XX_LED_RED_ON
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str r1, [r0]
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/* There is no SDRAM so flash the green LED. */
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flash_green:
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orr r1, r1, #EP93XX_LED_GREEN_ON
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str r1, [r0]
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ldr r2, =0x00010000
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flash_green_delay_1:
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subs r2, r2, #1
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bne flash_green_delay_1
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bic r1, r1, #EP93XX_LED_GREEN_ON
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str r1, [r0]
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ldr r2, =0x00010000
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flash_green_delay_2:
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subs r2, r2, #1
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bne flash_green_delay_2
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orr r1, r1, #EP93XX_LED_GREEN_ON
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str r1, [r0]
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ldr r2, =0x00010000
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flash_green_delay_3:
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subs r2, r2, #1
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bne flash_green_delay_3
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bic r1, r1, #EP93XX_LED_GREEN_ON
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str r1, [r0]
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ldr r2, =0x00050000
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flash_green_delay_4:
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subs r2, r2, #1
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bne flash_green_delay_4
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b flash_green
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ep93xx_sdram_done:
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ldr r1, =EP93XX_LED_DATA
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ldr r0, [r1]
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bic r0, r0, #EP93XX_LED_RED_ON
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str r0, [r1]
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/* Determine the size of the SDRAM. */
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mov r0, r11
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bl ep93xx_sdram_size
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/* Save the SDRAM characteristics. */
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mov r8, r0
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mov r9, r1
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mov r10, r2
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/* Compute total memory size into r1 */
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mul r1, r8, r10
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#ifdef CONFIG_EDB93XX_SDCS0
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ldr r2, [r0, #SDRAM_OFF_DEVCFG0]
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#endif
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#ifdef CONFIG_EDB93XX_SDCS1
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ldr r2, [r0, #SDRAM_OFF_DEVCFG1]
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#endif
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#ifdef CONFIG_EDB93XX_SDCS2
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ldr r2, [r0, #SDRAM_OFF_DEVCFG2]
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#endif
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#ifdef CONFIG_EDB93XX_SDCS3
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ldr r2, [r0, #SDRAM_OFF_DEVCFG3]
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#endif
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/* Consider small DRAM size as:
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* < 32Mb for 32bit bus
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* < 64Mb for 16bit bus
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*/
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tst r2, #EP93XX_SDRAMCTRL_DEVCFG_EXTBUSWIDTH
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moveq r1, r1, lsr #1
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cmp r1, #0x02000000
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#if defined(CONFIG_EDB9301)
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/* Set refresh counter to 20ms for small DRAM size, otherwise 9.6ms */
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movlt r1, #0x03f0
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movge r1, #0x01e0
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#else
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/* Set refresh counter to 30.7ms for small DRAM size, otherwise 15ms */
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movlt r1, #0x0600
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movge r1, #0x2f0
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#endif
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str r1, [r0, #SDRAM_OFF_REFRSHTIMR]
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/* Save the memory configuration information. */
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orr r0, r11, #UBOOT_MEMORYCNF_BANK_SIZE
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stmia r0, {r8-r11}
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mov lr, r6
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mov pc, lr
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