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https://github.com/brain-hackers/u-boot-brain
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3b621ccabd
On some x86 processors (like Intel Quark) the MTRR registers are not supported. This is reflected by the CPUID (EAX 01H) result EDX[12]. Accessing the MTRR registers on such processors will cause #GP so we must test the support flag before accessing MTRR MSRs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
108 lines
2.5 KiB
C
108 lines
2.5 KiB
C
/*
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* Copyright (c) 2014 Google, Inc
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*
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* From Coreboot file of the same name
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_MTRR_H
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#define _ASM_MTRR_H
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/* MTRR region types */
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#define MTRR_TYPE_UNCACHEABLE 0
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#define MTRR_TYPE_WRCOMB 1
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#define MTRR_TYPE_WRTHROUGH 4
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#define MTRR_TYPE_WRPROT 5
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#define MTRR_TYPE_WRBACK 6
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#define MTRR_TYPE_COUNT 7
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#define MTRR_CAP_MSR 0x0fe
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#define MTRR_DEF_TYPE_MSR 0x2ff
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#define MTRR_DEF_TYPE_EN (1 << 11)
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#define MTRR_DEF_TYPE_FIX_EN (1 << 10)
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#define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg))
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#define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1)
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#define MTRR_PHYS_MASK_VALID (1 << 11)
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#define MTRR_BASE_TYPE_MASK 0x7
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/* Number of MTRRs supported */
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#define MTRR_COUNT 8
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#if !defined(__ASSEMBLER__)
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/**
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* Information about the previous MTRR state, set up by mtrr_open()
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*
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* @deftype: Previous value of MTRR_DEF_TYPE_MSR
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* @enable_cache: true if cache was enabled
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*/
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struct mtrr_state {
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uint64_t deftype;
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bool enable_cache;
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};
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/**
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* mtrr_open() - Prepare to adjust MTRRs
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*
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* Use mtrr_open() passing in a structure - this function will init it. Then
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* when done, pass the same structure to mtrr_close() to re-enable MTRRs and
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* possibly the cache.
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*
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* @state: Empty structure to pass in to hold settings
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*/
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void mtrr_open(struct mtrr_state *state);
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/**
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* mtrr_open() - Clean up after adjusting MTRRs, and enable them
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*
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* This uses the structure containing information returned from mtrr_open().
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*
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* @state: Structure from mtrr_open()
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*/
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void mtrr_close(struct mtrr_state *state);
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/**
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* mtrr_add_request() - Add a new MTRR request
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*
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* This adds a request for a memory region to be set up in a particular way.
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*
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* @type: Requested type (MTRR_TYPE_)
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* @start: Start address
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* @size: Size
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*
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* @return: 0 on success, non-zero on failure
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*/
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int mtrr_add_request(int type, uint64_t start, uint64_t size);
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/**
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* mtrr_commit() - set up the MTRR registers based on current requests
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*
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* This sets up MTRRs for the available DRAM and the requests received so far.
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* It must be called with caches disabled.
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*
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* @do_caches: true if caches are currently on
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*
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* @return: 0 on success, non-zero on failure
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*/
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int mtrr_commit(bool do_caches);
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#endif
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#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
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# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
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#endif
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#if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE - 1)) != 0)
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# error "CONFIG_CACHE_ROM_SIZE is not a power of 2"
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#endif
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#define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12)
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#endif
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