mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 07:16:04 +09:00
1001502545
While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini <trini@konsulko.com>
127 lines
2.6 KiB
C
127 lines
2.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <ram.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/clock.h>
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#include <asm/arch-rockchip/periph.h>
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#include <asm/arch-rockchip/grf_rk3128.h>
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#include <asm/arch-rockchip/boot_mode.h>
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#include <asm/arch-rockchip/timer.h>
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#include <power/regulator.h>
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DECLARE_GLOBAL_DATA_PTR;
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__weak int rk_board_late_init(void)
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{
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return 0;
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}
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int board_late_init(void)
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{
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setup_boot_mode();
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return rk_board_late_init();
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}
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int board_init(void)
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{
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int ret = 0;
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rockchip_timer_init();
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ret = regulators_enable_boot_on(false);
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if (ret) {
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debug("%s: Cannot enable boot on regulator\n", __func__);
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return ret;
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}
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].size = 0x8400000;
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/* Reserve 0xe00000(14MB) for OPTEE with TA enabled, otherwise 2MB */
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gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE
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+ gd->bd->bi_dram[0].size + 0xe00000;
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gd->bd->bi_dram[1].size = gd->bd->bi_dram[0].start
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+ gd->ram_size - gd->bd->bi_dram[1].start;
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return 0;
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}
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#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
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#include <usb.h>
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#include <usb/dwc2_udc.h>
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static struct dwc2_plat_otg_data rk3128_otg_data = {
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.rx_fifo_sz = 512,
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.np_tx_fifo_sz = 16,
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.tx_fifo_sz = 128,
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};
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int board_usb_init(int index, enum usb_init_type init)
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{
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int node;
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const char *mode;
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bool matched = false;
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const void *blob = gd->fdt_blob;
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/* find the usb_otg node */
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node = fdt_node_offset_by_compatible(blob, -1,
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"rockchip,rk3128-usb");
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while (node > 0) {
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mode = fdt_getprop(blob, node, "dr_mode", NULL);
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if (mode && strcmp(mode, "otg") == 0) {
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matched = true;
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break;
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}
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node = fdt_node_offset_by_compatible(blob, node,
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"rockchip,rk3128-usb");
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}
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if (!matched) {
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debug("Not found usb_otg device\n");
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return -ENODEV;
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}
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rk3128_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
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return dwc2_udc_probe(&rk3128_otg_data);
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}
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int board_usb_cleanup(int index, enum usb_init_type init)
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{
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return 0;
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}
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#endif
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#if CONFIG_IS_ENABLED(FASTBOOT)
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int fastboot_set_reboot_flag(void)
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{
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struct rk3128_grf *grf;
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printf("Setting reboot to fastboot flag ...\n");
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grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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/* Set boot mode to fastboot */
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writel(BOOT_FASTBOOT, &grf->os_reg[0]);
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return 0;
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}
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#endif
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