mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-15 23:56:23 +09:00
0ff65eb99c
We don't have driver for the Intel Topcliff PCH Gigabit Ethernet controller for now, so enable the Intle E1000 NIC support, which can be plugged into any PCIe slot on the Crown Bay board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
56 lines
1.2 KiB
C
56 lines
1.2 KiB
C
/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <configs/x86-common.h>
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#define CONFIG_SYS_MONITOR_LEN (1 << 20)
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#define CONFIG_SYS_X86_START16 0xfffff800
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_X86_RESET_VECTOR
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_COREBOOT_SERIAL
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#define CONFIG_SMSC_LPC47M
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#define CONFIG_PCI_MEM_BUS 0x40000000
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#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
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#define CONFIG_PCI_MEM_SIZE 0x80000000
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#define CONFIG_PCI_PREF_BUS 0xc0000000
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#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS
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#define CONFIG_PCI_PREF_SIZE 0x20000000
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#define CONFIG_PCI_IO_BUS 0x2000
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#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
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#define CONFIG_PCI_IO_SIZE 0xe000
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#define CONFIG_SYS_EARLY_PCI_INIT
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#define CONFIG_PCI_PNP
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#define CONFIG_E1000
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#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \
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"stdout=serial\0" \
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"stderr=serial\0"
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#define CONFIG_SCSI_DEV_LIST \
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{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_SATA}
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#define CONFIG_SPI_FLASH_SST
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/* Video is not supported */
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#undef CONFIG_VIDEO
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#undef CONFIG_CFB_CONSOLE
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#endif /* __CONFIG_H */
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