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https://github.com/brain-hackers/u-boot-brain
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41575d8e4c
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
342 lines
10 KiB
C
342 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
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*/
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#include <common.h>
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#include <errno.h>
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#include <log.h>
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#include <malloc.h>
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#include <wait_bit.h>
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#include <dm.h>
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#include <reset-uclass.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <dt-bindings/reset/stih407-resets.h>
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#include <linux/bitops.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct sti_reset {
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const struct syscfg_reset_controller_data *data;
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};
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/**
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* Reset channel description for a system configuration register based
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* reset controller.
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*
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* @compatible: Compatible string of the syscon containing this
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* channel's control and ack (status) bits.
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* @reset_offset: Reset register offset in sysconf bank.
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* @reset_bit: Bit number in reset register.
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* @ack_offset: Ack reset register offset in syscon bank.
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* @ack_bit: Bit number in Ack reset register.
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* @deassert_cnt: incremented when reset is deasserted, reset can only be
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* asserted when equal to 0
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*/
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struct syscfg_reset_channel_data {
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const char *compatible;
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int reset_offset;
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int reset_bit;
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int ack_offset;
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int ack_bit;
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int deassert_cnt;
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};
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/**
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* Description of a system configuration register based reset controller.
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*
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* @wait_for_ack: The controller will wait for reset assert and de-assert to
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* be "ack'd" in a channel's ack field.
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* @active_low: Are the resets in this controller active low, i.e. clearing
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* the reset bit puts the hardware into reset.
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* @nr_channels: The number of reset channels in this controller.
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* @channels: An array of reset channel descriptions.
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*/
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struct syscfg_reset_controller_data {
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bool wait_for_ack;
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bool active_low;
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int nr_channels;
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struct syscfg_reset_channel_data *channels;
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};
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/* STiH407 Peripheral powerdown definitions. */
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static const char stih407_core[] = "st,stih407-core-syscfg";
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static const char stih407_sbc_reg[] = "st,stih407-sbc-reg-syscfg";
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static const char stih407_lpm[] = "st,stih407-lpm-syscfg";
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#define _SYSCFG_RST_CH(_c, _rr, _rb, _ar, _ab) \
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{ .compatible = _c, \
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.reset_offset = _rr, \
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.reset_bit = _rb, \
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.ack_offset = _ar, \
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.ack_bit = _ab, }
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#define _SYSCFG_RST_CH_NO_ACK(_c, _rr, _rb) \
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{ .compatible = _c, \
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.reset_offset = _rr, \
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.reset_bit = _rb, }
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#define STIH407_SRST_CORE(_reg, _bit) \
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_SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit)
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#define STIH407_SRST_SBC(_reg, _bit) \
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_SYSCFG_RST_CH_NO_ACK(stih407_sbc_reg, _reg, _bit)
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#define STIH407_SRST_LPM(_reg, _bit) \
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_SYSCFG_RST_CH_NO_ACK(stih407_lpm, _reg, _bit)
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#define STIH407_PDN_0(_bit) \
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_SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit)
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#define STIH407_PDN_1(_bit) \
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_SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit)
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#define STIH407_PDN_ETH(_bit, _stat) \
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_SYSCFG_RST_CH(stih407_sbc_reg, SYSCFG_4032, _bit, SYSSTAT_4520, _stat)
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/* Powerdown requests control 0 */
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#define SYSCFG_5000 0x0
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#define SYSSTAT_5500 0x7d0
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/* Powerdown requests control 1 (High Speed Links) */
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#define SYSCFG_5001 0x4
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#define SYSSTAT_5501 0x7d4
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/* Ethernet powerdown/status/reset */
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#define SYSCFG_4032 0x80
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#define SYSSTAT_4520 0x820
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#define SYSCFG_4002 0x8
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static struct syscfg_reset_channel_data stih407_powerdowns[] = {
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[STIH407_EMISS_POWERDOWN] = STIH407_PDN_0(1),
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[STIH407_NAND_POWERDOWN] = STIH407_PDN_0(0),
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[STIH407_USB3_POWERDOWN] = STIH407_PDN_1(6),
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[STIH407_USB2_PORT1_POWERDOWN] = STIH407_PDN_1(5),
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[STIH407_USB2_PORT0_POWERDOWN] = STIH407_PDN_1(4),
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[STIH407_PCIE1_POWERDOWN] = STIH407_PDN_1(3),
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[STIH407_PCIE0_POWERDOWN] = STIH407_PDN_1(2),
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[STIH407_SATA1_POWERDOWN] = STIH407_PDN_1(1),
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[STIH407_SATA0_POWERDOWN] = STIH407_PDN_1(0),
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[STIH407_ETH1_POWERDOWN] = STIH407_PDN_ETH(0, 2),
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};
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/* Reset Generator control 0/1 */
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#define SYSCFG_5128 0x200
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#define SYSCFG_5131 0x20c
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#define SYSCFG_5132 0x210
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#define LPM_SYSCFG_1 0x4 /* Softreset IRB & SBC UART */
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static struct syscfg_reset_channel_data stih407_softresets[] = {
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[STIH407_ETH1_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 4),
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[STIH407_MMC1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 3),
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[STIH407_USB2_PORT0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 28),
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[STIH407_USB2_PORT1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 29),
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[STIH407_PICOPHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 30),
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[STIH407_IRB_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 6),
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[STIH407_PCIE0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 6),
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[STIH407_PCIE1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 15),
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[STIH407_SATA0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 7),
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[STIH407_SATA1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 16),
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[STIH407_MIPHY0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 4),
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[STIH407_MIPHY1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 13),
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[STIH407_MIPHY2_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 22),
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[STIH407_SATA0_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 5),
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[STIH407_SATA1_PWR_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 14),
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[STIH407_DELTA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 3),
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[STIH407_BLITTER_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 10),
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[STIH407_HDTVOUT_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 11),
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[STIH407_HDQVDP_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 12),
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[STIH407_VDP_AUX_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 14),
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[STIH407_COMPO_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 15),
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[STIH407_HDMI_TX_PHY_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 21),
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[STIH407_JPEG_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 23),
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[STIH407_VP8_DEC_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 24),
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[STIH407_GPU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 30),
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[STIH407_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 0),
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[STIH407_ERAM_HVA_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5132, 1),
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[STIH407_LPM_SOFTRESET] = STIH407_SRST_SBC(SYSCFG_4002, 2),
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[STIH407_KEYSCAN_SOFTRESET] = STIH407_SRST_LPM(LPM_SYSCFG_1, 8),
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[STIH407_ST231_AUD_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 26),
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[STIH407_ST231_DMU_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 27),
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[STIH407_ST231_GP0_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5131, 28),
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[STIH407_ST231_GP1_SOFTRESET] = STIH407_SRST_CORE(SYSCFG_5128, 2),
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};
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/* PicoPHY reset/control */
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#define SYSCFG_5061 0x0f4
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static struct syscfg_reset_channel_data stih407_picophyresets[] = {
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[STIH407_PICOPHY0_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 5),
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[STIH407_PICOPHY1_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 6),
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[STIH407_PICOPHY2_RESET] = STIH407_SRST_CORE(SYSCFG_5061, 7),
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};
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static const struct
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syscfg_reset_controller_data stih407_powerdown_controller = {
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.wait_for_ack = true,
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.nr_channels = ARRAY_SIZE(stih407_powerdowns),
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.channels = stih407_powerdowns,
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};
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static const struct
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syscfg_reset_controller_data stih407_softreset_controller = {
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.wait_for_ack = false,
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.active_low = true,
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.nr_channels = ARRAY_SIZE(stih407_softresets),
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.channels = stih407_softresets,
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};
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static const struct
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syscfg_reset_controller_data stih407_picophyreset_controller = {
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.wait_for_ack = false,
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.nr_channels = ARRAY_SIZE(stih407_picophyresets),
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.channels = stih407_picophyresets,
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};
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phys_addr_t sti_reset_get_regmap(const char *compatible)
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{
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struct udevice *syscon;
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struct regmap *regmap;
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int node, ret;
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node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
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compatible);
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if (node < 0) {
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pr_err("unable to find %s node\n", compatible);
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return node;
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}
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ret = uclass_get_device_by_of_offset(UCLASS_SYSCON, node, &syscon);
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if (ret) {
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pr_err("%s: uclass_get_device_by_of_offset failed: %d\n",
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__func__, ret);
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return ret;
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}
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regmap = syscon_get_regmap(syscon);
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if (!regmap) {
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pr_err("unable to get regmap for %s\n", syscon->name);
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return -ENODEV;
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}
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return regmap->ranges[0].start;
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}
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static int sti_reset_program_hw(struct reset_ctl *reset_ctl, int assert)
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{
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struct udevice *dev = reset_ctl->dev;
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struct syscfg_reset_controller_data *reset_desc =
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(struct syscfg_reset_controller_data *)(dev->driver_data);
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struct syscfg_reset_channel_data *ch;
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phys_addr_t base;
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u32 ctrl_val = reset_desc->active_low ? !assert : !!assert;
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void __iomem *reg;
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/* check if reset id is inside available range */
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if (reset_ctl->id >= reset_desc->nr_channels)
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return -EINVAL;
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/* get reset sysconf register base address */
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base = sti_reset_get_regmap(reset_desc->channels[reset_ctl->id].compatible);
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ch = &reset_desc->channels[reset_ctl->id];
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/* check the deassert counter to assert reset when it reaches 0 */
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if (!assert) {
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ch->deassert_cnt++;
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if (ch->deassert_cnt > 1)
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return 0;
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} else {
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if (ch->deassert_cnt > 0) {
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ch->deassert_cnt--;
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if (ch->deassert_cnt > 0)
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return 0;
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} else
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pr_err("Reset balancing error: reset_ctl=%p dev=%p id=%lu\n",
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reset_ctl, reset_ctl->dev, reset_ctl->id);
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}
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reg = (void __iomem *)base + ch->reset_offset;
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if (ctrl_val)
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generic_set_bit(ch->reset_bit, reg);
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else
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generic_clear_bit(ch->reset_bit, reg);
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if (!reset_desc->wait_for_ack)
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return 0;
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reg = (void __iomem *)base + ch->ack_offset;
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if (wait_for_bit_le32(reg, BIT(ch->ack_bit), ctrl_val,
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1000, false)) {
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pr_err("Stuck on waiting ack reset_ctl=%p dev=%p id=%lu\n",
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reset_ctl, reset_ctl->dev, reset_ctl->id);
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return -ETIMEDOUT;
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}
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return 0;
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}
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static int sti_reset_request(struct reset_ctl *reset_ctl)
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{
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return 0;
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}
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static int sti_reset_free(struct reset_ctl *reset_ctl)
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{
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return 0;
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}
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static int sti_reset_assert(struct reset_ctl *reset_ctl)
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{
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return sti_reset_program_hw(reset_ctl, true);
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}
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static int sti_reset_deassert(struct reset_ctl *reset_ctl)
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{
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return sti_reset_program_hw(reset_ctl, false);
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}
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struct reset_ops sti_reset_ops = {
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.request = sti_reset_request,
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.rfree = sti_reset_free,
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.rst_assert = sti_reset_assert,
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.rst_deassert = sti_reset_deassert,
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};
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static int sti_reset_probe(struct udevice *dev)
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{
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struct sti_reset *priv = dev_get_priv(dev);
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priv->data = (void *)dev_get_driver_data(dev);
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return 0;
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}
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static const struct udevice_id sti_reset_ids[] = {
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{
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.compatible = "st,stih407-picophyreset",
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.data = (ulong)&stih407_picophyreset_controller,
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},
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{
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.compatible = "st,stih407-powerdown",
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.data = (ulong)&stih407_powerdown_controller,
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},
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{
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.compatible = "st,stih407-softreset",
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.data = (ulong)&stih407_softreset_controller,
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},
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{ }
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};
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U_BOOT_DRIVER(sti_reset) = {
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.name = "sti_reset",
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.id = UCLASS_RESET,
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.of_match = sti_reset_ids,
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.probe = sti_reset_probe,
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.priv_auto = sizeof(struct sti_reset),
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.ops = &sti_reset_ops,
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};
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