mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
caa4daa2ae
We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
305 lines
7.7 KiB
C
305 lines
7.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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* Andy Fleming <afleming@gmail.com>
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* Roy Zang <tie-fei.zang@freescale.com>
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* Some part is taken from tsec.c
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <asm/io.h>
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#include <fsl_memac.h>
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#include <fm_eth.h>
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#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
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#define memac_out_32(a, v) out_le32(a, v)
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#define memac_clrbits_32(a, v) clrbits_le32(a, v)
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#define memac_setbits_32(a, v) setbits_le32(a, v)
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#else
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#define memac_out_32(a, v) out_be32(a, v)
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#define memac_clrbits_32(a, v) clrbits_be32(a, v)
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#define memac_setbits_32(a, v) setbits_be32(a, v)
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#endif
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#ifdef CONFIG_DM_ETH
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struct fm_mdio_priv {
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struct memac_mdio_controller *regs;
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};
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#endif
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static u32 memac_in_32(u32 *reg)
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{
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#ifdef CONFIG_SYS_MEMAC_LITTLE_ENDIAN
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return in_le32(reg);
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#else
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return in_be32(reg);
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#endif
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}
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/*
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* Write value to the PHY for this device to the register at regnum, waiting
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* until the write is done before it returns. All PHY configuration has to be
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* done through the TSEC1 MIIM regs
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*/
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int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
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int regnum, u16 value)
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{
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struct memac_mdio_controller *regs;
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u32 mdio_ctl;
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u32 c45 = 1; /* Default to 10G interface */
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#ifndef CONFIG_DM_ETH
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regs = bus->priv;
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#else
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struct fm_mdio_priv *priv;
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if (!bus->priv)
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return -EINVAL;
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priv = dev_get_priv(bus->priv);
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regs = priv->regs;
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debug("memac_mdio_write(regs %p, port %d, dev %d, reg %d, val %#x)\n",
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regs, port_addr, dev_addr, regnum, value);
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#endif
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if (dev_addr == MDIO_DEVAD_NONE) {
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c45 = 0; /* clause 22 */
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dev_addr = regnum & 0x1f;
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memac_clrbits_32(®s->mdio_stat, MDIO_STAT_ENC);
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} else
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memac_setbits_32(®s->mdio_stat, MDIO_STAT_ENC);
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/* Wait till the bus is free */
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while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Set the port and dev addr */
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mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
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memac_out_32(®s->mdio_ctl, mdio_ctl);
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/* Set the register address */
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if (c45)
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memac_out_32(®s->mdio_addr, regnum & 0xffff);
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/* Wait till the bus is free */
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while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Write the value to the register */
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memac_out_32(®s->mdio_data, MDIO_DATA(value));
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/* Wait till the MDIO write is complete */
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while ((memac_in_32(®s->mdio_data)) & MDIO_DATA_BSY)
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;
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return 0;
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}
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/*
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* Reads from register regnum in the PHY for device dev, returning the value.
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* Clears miimcom first. All PHY configuration has to be done through the
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* TSEC1 MIIM regs
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*/
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int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
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int regnum)
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{
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struct memac_mdio_controller *regs;
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u32 mdio_ctl;
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u32 c45 = 1;
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#ifndef CONFIG_DM_ETH
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regs = bus->priv;
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#else
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struct fm_mdio_priv *priv;
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if (!bus->priv)
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return -EINVAL;
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priv = dev_get_priv(bus->priv);
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regs = priv->regs;
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#endif
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if (dev_addr == MDIO_DEVAD_NONE) {
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#ifndef CONFIG_DM_ETH
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if (!strcmp(bus->name, DEFAULT_FM_TGEC_MDIO_NAME))
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return 0xffff;
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#endif
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c45 = 0; /* clause 22 */
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dev_addr = regnum & 0x1f;
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memac_clrbits_32(®s->mdio_stat, MDIO_STAT_ENC);
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} else
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memac_setbits_32(®s->mdio_stat, MDIO_STAT_ENC);
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/* Wait till the bus is free */
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while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Set the Port and Device Addrs */
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mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
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memac_out_32(®s->mdio_ctl, mdio_ctl);
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/* Set the register address */
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if (c45)
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memac_out_32(®s->mdio_addr, regnum & 0xffff);
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/* Wait till the bus is free */
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while ((memac_in_32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Initiate the read */
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mdio_ctl |= MDIO_CTL_READ;
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memac_out_32(®s->mdio_ctl, mdio_ctl);
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/* Wait till the MDIO write is complete */
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while ((memac_in_32(®s->mdio_data)) & MDIO_DATA_BSY)
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;
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/* Return all Fs if nothing was there */
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if (memac_in_32(®s->mdio_stat) & MDIO_STAT_RD_ER)
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return 0xffff;
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return memac_in_32(®s->mdio_data) & 0xffff;
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}
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int memac_mdio_reset(struct mii_dev *bus)
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{
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return 0;
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}
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#ifndef CONFIG_DM_ETH
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int fm_memac_mdio_init(struct bd_info *bis, struct memac_mdio_info *info)
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{
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate FM TGEC MDIO bus\n");
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return -1;
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}
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bus->read = memac_mdio_read;
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bus->write = memac_mdio_write;
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bus->reset = memac_mdio_reset;
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strcpy(bus->name, info->name);
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bus->priv = info->regs;
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/*
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* On some platforms like B4860, default value of MDIO_CLK_DIV bits
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* in mdio_stat(mdio_cfg) register generates MDIO clock too high
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* (much higher than 2.5MHz), violating the IEEE specs.
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* On other platforms like T1040, default value of MDIO_CLK_DIV bits
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* is zero, so MDIO clock is disabled.
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* So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
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* be properly initialized.
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* NEG bit default should be '1' as per FMAN-v3 RM, but on platform
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* like T2080QDS, this bit default is '0', which leads to MDIO failure
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* on XAUI PHY, so set this bit definitely.
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*/
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memac_setbits_32(
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&((struct memac_mdio_controller *)info->regs)->mdio_stat,
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MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
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return mdio_register(bus);
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}
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#else /* CONFIG_DM_ETH */
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#if defined(CONFIG_PHYLIB) && defined(CONFIG_DM_MDIO)
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static int fm_mdio_read(struct udevice *dev, int addr, int devad, int reg)
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{
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struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
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NULL;
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if (pdata && pdata->mii_bus)
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return memac_mdio_read(pdata->mii_bus, addr, devad, reg);
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return -1;
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}
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static int fm_mdio_write(struct udevice *dev, int addr, int devad, int reg,
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u16 val)
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{
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struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
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NULL;
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if (pdata && pdata->mii_bus)
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return memac_mdio_write(pdata->mii_bus, addr, devad, reg, val);
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return -1;
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}
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static int fm_mdio_reset(struct udevice *dev)
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{
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struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
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NULL;
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if (pdata && pdata->mii_bus)
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return memac_mdio_reset(pdata->mii_bus);
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return -1;
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}
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static const struct mdio_ops fm_mdio_ops = {
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.read = fm_mdio_read,
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.write = fm_mdio_write,
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.reset = fm_mdio_reset,
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};
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static const struct udevice_id fm_mdio_ids[] = {
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{ .compatible = "fsl,fman-memac-mdio" },
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{}
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};
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static int fm_mdio_probe(struct udevice *dev)
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{
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struct fm_mdio_priv *priv = (dev) ? dev_get_priv(dev) : NULL;
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struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
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NULL;
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if (!dev) {
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printf("%s dev = NULL\n", __func__);
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return -1;
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}
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if (!priv) {
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printf("dev_get_priv(dev %p) = NULL\n", dev);
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return -1;
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}
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priv->regs = (void *)(uintptr_t)dev_read_addr(dev);
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debug("%s priv %p @ regs %p, pdata %p\n", __func__,
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priv, priv->regs, pdata);
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/*
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* On some platforms like B4860, default value of MDIO_CLK_DIV bits
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* in mdio_stat(mdio_cfg) register generates MDIO clock too high
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* (much higher than 2.5MHz), violating the IEEE specs.
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* On other platforms like T1040, default value of MDIO_CLK_DIV bits
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* is zero, so MDIO clock is disabled.
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* So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
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* be properly initialized.
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* The default NEG bit should be '1' as per FMANv3 RM, but on platforms
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* like T2080QDS, this bit default is '0', which leads to MDIO failure
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* on XAUI PHY, so set this bit definitely.
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*/
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if (priv && priv->regs && priv->regs->mdio_stat)
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memac_setbits_32(&priv->regs->mdio_stat,
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MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
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return 0;
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}
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static int fm_mdio_remove(struct udevice *dev)
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{
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return 0;
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}
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U_BOOT_DRIVER(fman_mdio) = {
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.name = "fman_mdio",
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.id = UCLASS_MDIO,
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.of_match = fm_mdio_ids,
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.probe = fm_mdio_probe,
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.remove = fm_mdio_remove,
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.ops = &fm_mdio_ops,
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.priv_auto = sizeof(struct fm_mdio_priv),
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.plat_auto = sizeof(struct mdio_perdev_priv),
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};
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#endif /* CONFIG_PHYLIB && CONFIG_DM_MDIO */
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#endif /* CONFIG_DM_ETH */
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