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0fba27b690
Add psc information for k2g Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
52 lines
1.3 KiB
C
52 lines
1.3 KiB
C
/*
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* K2G: SoC definitions
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*
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* (C) Copyright 2015
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_HARDWARE_K2G_H
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#define __ASM_ARCH_HARDWARE_K2G_H
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#define KS2_NUM_DSPS 0
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/* Power and Sleep Controller (PSC) Domains */
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#define KS2_LPSC_ALWAYSON 0
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#define KS2_LPSC_PMMC 1
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#define KS2_LPSC_DEBUG 2
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#define KS2_LPSC_NSS 3
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#define KS2_LPSC_SA 4
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#define KS2_LPSC_TERANET 5
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#define KS2_LPSC_SYS_COMP 6
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#define KS2_LPSC_QSPI 7
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#define KS2_LPSC_MMC 8
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#define KS2_LPSC_GPMC 9
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#define KS2_LPSC_MLB 11
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#define KS2_LPSC_EHRPWM 12
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#define KS2_LPSC_EQEP 13
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#define KS2_LPSC_ECAP 14
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#define KS2_LPSC_MCASP 15
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#define KS2_LPSC_SR 16
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#define KS2_LPSC_MSMC 17
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#define KS2_LPSC_GEM 18
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#define KS2_LPSC_ARM 19
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#define KS2_LPSC_ASRC 20
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#define KS2_LPSC_ICSS 21
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#define KS2_LPSC_DSS 23
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#define KS2_LPSC_PCIE 24
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#define KS2_LPSC_USB_0 25
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#define KS2_LPSC_USB KS2_LPSC_USB_0
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#define KS2_LPSC_USB_1 26
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#define KS2_LPSC_DDR3 27
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#define KS2_LPSC_SPARE0_LPSC0 28
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#define KS2_LPSC_SPARE0_LPSC1 29
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#define KS2_LPSC_SPARE1_LPSC0 30
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#define KS2_LPSC_SPARE1_LPSC1 31
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#define KS2_LPSC_CPGMAC KS2_LPSC_NSS
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#define KS2_LPSC_CRYPTO KS2_LPSC_SA
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#endif /* __ASM_ARCH_HARDWARE_K2G_H */
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