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![Heiko Schocher](/assets/img/avatar_default.png)
add DM/DTS support for the UEC ethernet on QUICC Engine Block. Signed-off-by: Heiko Schocher <hs@denx.de> Patch-cc: Mario Six <mario.six@gdsys.cc> Patch-cc: Qiang Zhao <qiang.zhao@nxp.com> Patch-cc: Holger Brunck <holger.brunck@hitachi-powergrids.com> Patch-cc: Madalin Bucur <madalin.bucur@oss.nxp.com> Series-changes: 3 - revert: commit "3374264df97b" ("drivers: net: qe: deselect QE when DM_ETH is enabled") as now qe works with DM and DM_ETH support. - fix mailaddress from Holger Series-changes: 2 - add comments from Qiang Zhao: - add device node documentation - I did not drop the dm_qe_uec_phy.c and use drivers/net/fsl_mdio.c because using drivers/net/fsl_mdio.c leads in none existent udevice mdio@3320 instead boards with DM ETH support should use now this driver. - remove RFC tag Commit-notes: - I let the old none DM based implementation in code so boards should work with old implementation. This Code should be removed if all boards are converted to DM/DTS. - add the DM based qe uec driver under drivers/net/qe - Therefore copied the files uccf.c uccf.h uec.h from drivers/qe. So there are a lot of Codingstyle problems currently. I fix them in next version if this RFC patch is OK or it needs some changes. - The dm based driver code is now under drivers/net/qe/dm_qe_uec.c Used a lot of functions from drivers/qe/uec.c - seperated the PHY specific code into seperate file drivers/net/qe/dm_qe_uec_phy.c END
1168 lines
29 KiB
C
1168 lines
29 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* QE UEC ethernet controller driver
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*
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* based on drivers/qe/uec.c from NXP
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*
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* Copyright (C) 2020 Heiko Schocher <hs@denx.de>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <memalign.h>
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#include <miiphy.h>
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#include <asm/io.h>
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#include "dm_qe_uec.h"
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#define QE_UEC_DRIVER_NAME "ucc_geth"
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/* Default UTBIPAR SMI address */
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#ifndef CONFIG_UTBIPAR_INIT_TBIPA
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#define CONFIG_UTBIPAR_INIT_TBIPA 0x1F
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#endif
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static int uec_mac_enable(struct uec_priv *uec, comm_dir_e mode)
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{
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uec_t *uec_regs;
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u32 maccfg1;
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uec_regs = uec->uec_regs;
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maccfg1 = in_be32(&uec_regs->maccfg1);
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if (mode & COMM_DIR_TX) {
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maccfg1 |= MACCFG1_ENABLE_TX;
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out_be32(&uec_regs->maccfg1, maccfg1);
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uec->mac_tx_enabled = 1;
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}
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if (mode & COMM_DIR_RX) {
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maccfg1 |= MACCFG1_ENABLE_RX;
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out_be32(&uec_regs->maccfg1, maccfg1);
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uec->mac_rx_enabled = 1;
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}
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return 0;
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}
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static int uec_mac_disable(struct uec_priv *uec, comm_dir_e mode)
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{
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uec_t *uec_regs;
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u32 maccfg1;
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uec_regs = uec->uec_regs;
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maccfg1 = in_be32(&uec_regs->maccfg1);
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if (mode & COMM_DIR_TX) {
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maccfg1 &= ~MACCFG1_ENABLE_TX;
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out_be32(&uec_regs->maccfg1, maccfg1);
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uec->mac_tx_enabled = 0;
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}
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if (mode & COMM_DIR_RX) {
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maccfg1 &= ~MACCFG1_ENABLE_RX;
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out_be32(&uec_regs->maccfg1, maccfg1);
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uec->mac_rx_enabled = 0;
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}
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return 0;
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}
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static int uec_restart_tx(struct uec_priv *uec)
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{
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struct uec_inf *ui = uec->uec_info;
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u32 cecr_subblock;
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cecr_subblock = ucc_fast_get_qe_cr_subblock(ui->uf_info.ucc_num);
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qe_issue_cmd(QE_RESTART_TX, cecr_subblock,
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(u8)QE_CR_PROTOCOL_ETHERNET, 0);
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uec->grace_stopped_tx = 0;
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return 0;
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}
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static int uec_restart_rx(struct uec_priv *uec)
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{
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struct uec_inf *ui = uec->uec_info;
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u32 cecr_subblock;
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cecr_subblock = ucc_fast_get_qe_cr_subblock(ui->uf_info.ucc_num);
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qe_issue_cmd(QE_RESTART_RX, cecr_subblock,
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(u8)QE_CR_PROTOCOL_ETHERNET, 0);
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uec->grace_stopped_rx = 0;
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return 0;
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}
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static int uec_open(struct uec_priv *uec, comm_dir_e mode)
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{
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struct ucc_fast_priv *uccf;
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uccf = uec->uccf;
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/* check if the UCC number is in range. */
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if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
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printf("%s: ucc_num out of range.\n", __func__);
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return -EINVAL;
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}
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/* Enable MAC */
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uec_mac_enable(uec, mode);
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/* Enable UCC fast */
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ucc_fast_enable(uccf, mode);
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/* RISC microcode start */
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if ((mode & COMM_DIR_TX) && uec->grace_stopped_tx)
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uec_restart_tx(uec);
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if ((mode & COMM_DIR_RX) && uec->grace_stopped_rx)
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uec_restart_rx(uec);
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return 0;
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}
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static int uec_set_mac_if_mode(struct uec_priv *uec)
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{
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struct uec_inf *uec_info = uec->uec_info;
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phy_interface_t enet_if_mode;
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uec_t *uec_regs;
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u32 upsmr;
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u32 maccfg2;
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uec_regs = uec->uec_regs;
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enet_if_mode = uec_info->enet_interface_type;
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maccfg2 = in_be32(&uec_regs->maccfg2);
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maccfg2 &= ~MACCFG2_INTERFACE_MODE_MASK;
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upsmr = in_be32(&uec->uccf->uf_regs->upsmr);
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upsmr &= ~(UPSMR_RPM | UPSMR_TBIM | UPSMR_R10M | UPSMR_RMM);
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switch (uec_info->speed) {
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case SPEED_10:
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maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
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switch (enet_if_mode) {
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case PHY_INTERFACE_MODE_MII:
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break;
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case PHY_INTERFACE_MODE_RGMII:
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upsmr |= (UPSMR_RPM | UPSMR_R10M);
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break;
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case PHY_INTERFACE_MODE_RMII:
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upsmr |= (UPSMR_R10M | UPSMR_RMM);
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break;
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default:
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return -EINVAL;
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}
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break;
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case SPEED_100:
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maccfg2 |= MACCFG2_INTERFACE_MODE_NIBBLE;
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switch (enet_if_mode) {
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case PHY_INTERFACE_MODE_MII:
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break;
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case PHY_INTERFACE_MODE_RGMII:
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upsmr |= UPSMR_RPM;
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break;
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case PHY_INTERFACE_MODE_RMII:
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upsmr |= UPSMR_RMM;
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break;
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default:
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return -EINVAL;
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}
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break;
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case SPEED_1000:
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maccfg2 |= MACCFG2_INTERFACE_MODE_BYTE;
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switch (enet_if_mode) {
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case PHY_INTERFACE_MODE_GMII:
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break;
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case PHY_INTERFACE_MODE_TBI:
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upsmr |= UPSMR_TBIM;
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break;
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case PHY_INTERFACE_MODE_RTBI:
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upsmr |= (UPSMR_RPM | UPSMR_TBIM);
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break;
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII:
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upsmr |= UPSMR_RPM;
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break;
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case PHY_INTERFACE_MODE_SGMII:
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upsmr |= UPSMR_SGMM;
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break;
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default:
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return -EINVAL;
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}
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break;
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default:
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return -EINVAL;
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}
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out_be32(&uec_regs->maccfg2, maccfg2);
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out_be32(&uec->uccf->uf_regs->upsmr, upsmr);
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return 0;
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}
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static int qe_uec_start(struct udevice *dev)
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{
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struct qe_uec_priv *priv = dev_get_priv(dev);
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struct uec_priv *uec = priv->uec;
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struct phy_device *phydev = priv->phydev;
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struct uec_inf *uec_info = uec->uec_info;
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int err;
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if (!phydev)
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return -ENODEV;
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/* Setup MAC interface mode */
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genphy_update_link(phydev);
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genphy_parse_link(phydev);
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uec_info->speed = phydev->speed;
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uec_set_mac_if_mode(uec);
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err = uec_open(uec, COMM_DIR_RX_AND_TX);
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if (err) {
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printf("%s: cannot enable UEC device\n", dev->name);
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return -EINVAL;
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}
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return (phydev->link ? 0 : -EINVAL);
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}
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static int qe_uec_send(struct udevice *dev, void *packet, int length)
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{
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struct qe_uec_priv *priv = dev_get_priv(dev);
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struct uec_priv *uec = priv->uec;
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struct ucc_fast_priv *uccf = uec->uccf;
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struct buffer_descriptor *bd;
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u16 status;
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int i;
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int result = 0;
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uccf = uec->uccf;
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bd = uec->tx_bd;
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/* Find an empty TxBD */
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for (i = 0; BD_STATUS(bd) & TX_BD_READY; i++) {
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if (i > 0x100000) {
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printf("%s: tx buffer not ready\n", dev->name);
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return result;
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}
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}
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/* Init TxBD */
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BD_DATA_SET(bd, packet);
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BD_LENGTH_SET(bd, length);
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status = BD_STATUS(bd);
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status &= BD_WRAP;
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status |= (TX_BD_READY | TX_BD_LAST);
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BD_STATUS_SET(bd, status);
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/* Tell UCC to transmit the buffer */
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ucc_fast_transmit_on_demand(uccf);
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/* Wait for buffer to be transmitted */
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for (i = 0; BD_STATUS(bd) & TX_BD_READY; i++) {
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if (i > 0x100000) {
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printf("%s: tx error\n", dev->name);
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return result;
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}
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}
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/* Ok, the buffer be transimitted */
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BD_ADVANCE(bd, status, uec->p_tx_bd_ring);
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uec->tx_bd = bd;
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result = 1;
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return result;
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}
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/*
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* Receive frame:
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* - wait for the next BD to get ready bit set
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* - clean up the descriptor
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* - move on and indicate to HW that the cleaned BD is available for Rx
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*/
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static int qe_uec_recv(struct udevice *dev, int flags, uchar **packetp)
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{
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struct qe_uec_priv *priv = dev_get_priv(dev);
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struct uec_priv *uec = priv->uec;
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struct buffer_descriptor *bd;
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u16 status;
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u16 len = 0;
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u8 *data;
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*packetp = memalign(ARCH_DMA_MINALIGN, MAX_RXBUF_LEN);
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if (*packetp == 0) {
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printf("%s: error allocating packetp\n", __func__);
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return -ENOMEM;
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}
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bd = uec->rx_bd;
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status = BD_STATUS(bd);
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while (!(status & RX_BD_EMPTY)) {
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if (!(status & RX_BD_ERROR)) {
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data = BD_DATA(bd);
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len = BD_LENGTH(bd);
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memcpy(*packetp, (char *)data, len);
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} else {
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printf("%s: Rx error\n", dev->name);
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}
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status &= BD_CLEAN;
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BD_LENGTH_SET(bd, 0);
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BD_STATUS_SET(bd, status | RX_BD_EMPTY);
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BD_ADVANCE(bd, status, uec->p_rx_bd_ring);
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status = BD_STATUS(bd);
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}
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uec->rx_bd = bd;
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return len;
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}
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static int uec_graceful_stop_tx(struct uec_priv *uec)
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{
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ucc_fast_t *uf_regs;
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u32 cecr_subblock;
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u32 ucce;
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uf_regs = uec->uccf->uf_regs;
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/* Clear the grace stop event */
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out_be32(&uf_regs->ucce, UCCE_GRA);
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/* Issue host command */
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cecr_subblock =
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ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
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qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock,
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(u8)QE_CR_PROTOCOL_ETHERNET, 0);
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/* Wait for command to complete */
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do {
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ucce = in_be32(&uf_regs->ucce);
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} while (!(ucce & UCCE_GRA));
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uec->grace_stopped_tx = 1;
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return 0;
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}
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static int uec_graceful_stop_rx(struct uec_priv *uec)
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{
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u32 cecr_subblock;
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u8 ack;
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if (!uec->p_rx_glbl_pram) {
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printf("%s: No init rx global parameter\n", __func__);
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return -EINVAL;
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}
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/* Clear acknowledge bit */
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ack = uec->p_rx_glbl_pram->rxgstpack;
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ack &= ~GRACEFUL_STOP_ACKNOWLEDGE_RX;
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uec->p_rx_glbl_pram->rxgstpack = ack;
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/* Keep issuing cmd and checking ack bit until it is asserted */
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do {
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/* Issue host command */
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cecr_subblock =
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ucc_fast_get_qe_cr_subblock(uec->uec_info->uf_info.ucc_num);
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qe_issue_cmd(QE_GRACEFUL_STOP_RX, cecr_subblock,
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(u8)QE_CR_PROTOCOL_ETHERNET, 0);
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ack = uec->p_rx_glbl_pram->rxgstpack;
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} while (!(ack & GRACEFUL_STOP_ACKNOWLEDGE_RX));
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uec->grace_stopped_rx = 1;
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return 0;
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}
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static int uec_stop(struct uec_priv *uec, comm_dir_e mode)
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{
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/* check if the UCC number is in range. */
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if (uec->uec_info->uf_info.ucc_num >= UCC_MAX_NUM) {
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printf("%s: ucc_num out of range.\n", __func__);
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return -EINVAL;
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}
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/* Stop any transmissions */
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if ((mode & COMM_DIR_TX) && !uec->grace_stopped_tx)
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uec_graceful_stop_tx(uec);
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/* Stop any receptions */
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if ((mode & COMM_DIR_RX) && !uec->grace_stopped_rx)
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uec_graceful_stop_rx(uec);
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/* Disable the UCC fast */
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ucc_fast_disable(uec->uccf, mode);
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/* Disable the MAC */
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uec_mac_disable(uec, mode);
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return 0;
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}
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static void qe_uec_stop(struct udevice *dev)
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{
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struct qe_uec_priv *priv = dev_get_priv(dev);
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struct uec_priv *uec = priv->uec;
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uec_stop(uec, COMM_DIR_RX_AND_TX);
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}
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static int qe_uec_set_hwaddr(struct udevice *dev)
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{
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struct qe_uec_priv *priv = dev_get_priv(dev);
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struct eth_pdata *pdata = dev_get_platdata(dev);
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struct uec_priv *uec = priv->uec;
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uec_t *uec_regs = uec->uec_regs;
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uchar *mac = pdata->enetaddr;
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u32 mac_addr1;
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u32 mac_addr2;
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/*
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* if a station address of 0x12345678ABCD, perform a write to
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* MACSTNADDR1 of 0xCDAB7856,
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* MACSTNADDR2 of 0x34120000
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*/
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mac_addr1 = (mac[5] << 24) | (mac[4] << 16) |
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(mac[3] << 8) | (mac[2]);
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out_be32(&uec_regs->macstnaddr1, mac_addr1);
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mac_addr2 = ((mac[1] << 24) | (mac[0] << 16)) & 0xffff0000;
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out_be32(&uec_regs->macstnaddr2, mac_addr2);
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return 0;
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}
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static int qe_uec_free_pkt(struct udevice *dev, uchar *packet, int length)
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{
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if (packet)
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free(packet);
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return 0;
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}
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static const struct eth_ops qe_uec_eth_ops = {
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.start = qe_uec_start,
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.send = qe_uec_send,
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.recv = qe_uec_recv,
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.free_pkt = qe_uec_free_pkt,
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.stop = qe_uec_stop,
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.write_hwaddr = qe_uec_set_hwaddr,
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};
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static int uec_convert_threads_num(enum uec_num_of_threads threads_num,
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int *threads_num_ret)
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{
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int num_threads_numerica;
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switch (threads_num) {
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case UEC_NUM_OF_THREADS_1:
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num_threads_numerica = 1;
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break;
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case UEC_NUM_OF_THREADS_2:
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num_threads_numerica = 2;
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break;
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case UEC_NUM_OF_THREADS_4:
|
|
num_threads_numerica = 4;
|
|
break;
|
|
case UEC_NUM_OF_THREADS_6:
|
|
num_threads_numerica = 6;
|
|
break;
|
|
case UEC_NUM_OF_THREADS_8:
|
|
num_threads_numerica = 8;
|
|
break;
|
|
default:
|
|
printf("%s: Bad number of threads value.",
|
|
__func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
*threads_num_ret = num_threads_numerica;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void uec_init_tx_parameter(struct uec_priv *uec, int num_threads_tx)
|
|
{
|
|
struct uec_inf *uec_info;
|
|
u32 end_bd;
|
|
u8 bmrx = 0;
|
|
int i;
|
|
|
|
uec_info = uec->uec_info;
|
|
|
|
/* Alloc global Tx parameter RAM page */
|
|
uec->tx_glbl_pram_offset =
|
|
qe_muram_alloc(sizeof(struct uec_tx_global_pram),
|
|
UEC_TX_GLOBAL_PRAM_ALIGNMENT);
|
|
uec->p_tx_glbl_pram = (struct uec_tx_global_pram *)
|
|
qe_muram_addr(uec->tx_glbl_pram_offset);
|
|
|
|
/* Zero the global Tx prameter RAM */
|
|
memset(uec->p_tx_glbl_pram, 0, sizeof(struct uec_tx_global_pram));
|
|
|
|
/* Init global Tx parameter RAM */
|
|
|
|
/* TEMODER, RMON statistics disable, one Tx queue */
|
|
out_be16(&uec->p_tx_glbl_pram->temoder, TEMODER_INIT_VALUE);
|
|
|
|
/* SQPTR */
|
|
uec->send_q_mem_reg_offset =
|
|
qe_muram_alloc(sizeof(struct uec_send_queue_qd),
|
|
UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT);
|
|
uec->p_send_q_mem_reg = (struct uec_send_queue_mem_region *)
|
|
qe_muram_addr(uec->send_q_mem_reg_offset);
|
|
out_be32(&uec->p_tx_glbl_pram->sqptr, uec->send_q_mem_reg_offset);
|
|
|
|
/* Setup the table with TxBDs ring */
|
|
end_bd = (u32)uec->p_tx_bd_ring + (uec_info->tx_bd_ring_len - 1)
|
|
* SIZEOFBD;
|
|
out_be32(&uec->p_send_q_mem_reg->sqqd[0].bd_ring_base,
|
|
(u32)(uec->p_tx_bd_ring));
|
|
out_be32(&uec->p_send_q_mem_reg->sqqd[0].last_bd_completed_address,
|
|
end_bd);
|
|
|
|
/* Scheduler Base Pointer, we have only one Tx queue, no need it */
|
|
out_be32(&uec->p_tx_glbl_pram->schedulerbasepointer, 0);
|
|
|
|
/* TxRMON Base Pointer, TxRMON disable, we don't need it */
|
|
out_be32(&uec->p_tx_glbl_pram->txrmonbaseptr, 0);
|
|
|
|
/* TSTATE, global snooping, big endian, the CSB bus selected */
|
|
bmrx = BMR_INIT_VALUE;
|
|
out_be32(&uec->p_tx_glbl_pram->tstate, ((u32)(bmrx) << BMR_SHIFT));
|
|
|
|
/* IPH_Offset */
|
|
for (i = 0; i < MAX_IPH_OFFSET_ENTRY; i++)
|
|
out_8(&uec->p_tx_glbl_pram->iphoffset[i], 0);
|
|
|
|
/* VTAG table */
|
|
for (i = 0; i < UEC_TX_VTAG_TABLE_ENTRY_MAX; i++)
|
|
out_be32(&uec->p_tx_glbl_pram->vtagtable[i], 0);
|
|
|
|
/* TQPTR */
|
|
uec->thread_dat_tx_offset =
|
|
qe_muram_alloc(num_threads_tx *
|
|
sizeof(struct uec_thread_data_tx) +
|
|
32 * (num_threads_tx == 1),
|
|
UEC_THREAD_DATA_ALIGNMENT);
|
|
|
|
uec->p_thread_data_tx = (struct uec_thread_data_tx *)
|
|
qe_muram_addr(uec->thread_dat_tx_offset);
|
|
out_be32(&uec->p_tx_glbl_pram->tqptr, uec->thread_dat_tx_offset);
|
|
}
|
|
|
|
static void uec_init_rx_parameter(struct uec_priv *uec, int num_threads_rx)
|
|
{
|
|
u8 bmrx = 0;
|
|
int i;
|
|
struct uec_82xx_add_filtering_pram *p_af_pram;
|
|
|
|
/* Allocate global Rx parameter RAM page */
|
|
uec->rx_glbl_pram_offset =
|
|
qe_muram_alloc(sizeof(struct uec_rx_global_pram),
|
|
UEC_RX_GLOBAL_PRAM_ALIGNMENT);
|
|
uec->p_rx_glbl_pram = (struct uec_rx_global_pram *)
|
|
qe_muram_addr(uec->rx_glbl_pram_offset);
|
|
|
|
/* Zero Global Rx parameter RAM */
|
|
memset(uec->p_rx_glbl_pram, 0, sizeof(struct uec_rx_global_pram));
|
|
|
|
/* Init global Rx parameter RAM */
|
|
/*
|
|
* REMODER, Extended feature mode disable, VLAN disable,
|
|
* LossLess flow control disable, Receive firmware statisic disable,
|
|
* Extended address parsing mode disable, One Rx queues,
|
|
* Dynamic maximum/minimum frame length disable, IP checksum check
|
|
* disable, IP address alignment disable
|
|
*/
|
|
out_be32(&uec->p_rx_glbl_pram->remoder, REMODER_INIT_VALUE);
|
|
|
|
/* RQPTR */
|
|
uec->thread_dat_rx_offset =
|
|
qe_muram_alloc(num_threads_rx *
|
|
sizeof(struct uec_thread_data_rx),
|
|
UEC_THREAD_DATA_ALIGNMENT);
|
|
uec->p_thread_data_rx = (struct uec_thread_data_rx *)
|
|
qe_muram_addr(uec->thread_dat_rx_offset);
|
|
out_be32(&uec->p_rx_glbl_pram->rqptr, uec->thread_dat_rx_offset);
|
|
|
|
/* Type_or_Len */
|
|
out_be16(&uec->p_rx_glbl_pram->typeorlen, 3072);
|
|
|
|
/* RxRMON base pointer, we don't need it */
|
|
out_be32(&uec->p_rx_glbl_pram->rxrmonbaseptr, 0);
|
|
|
|
/* IntCoalescingPTR, we don't need it, no interrupt */
|
|
out_be32(&uec->p_rx_glbl_pram->intcoalescingptr, 0);
|
|
|
|
/* RSTATE, global snooping, big endian, the CSB bus selected */
|
|
bmrx = BMR_INIT_VALUE;
|
|
out_8(&uec->p_rx_glbl_pram->rstate, bmrx);
|
|
|
|
/* MRBLR */
|
|
out_be16(&uec->p_rx_glbl_pram->mrblr, MAX_RXBUF_LEN);
|
|
|
|
/* RBDQPTR */
|
|
uec->rx_bd_qs_tbl_offset =
|
|
qe_muram_alloc(sizeof(struct uec_rx_bd_queues_entry) +
|
|
sizeof(struct uec_rx_pref_bds),
|
|
UEC_RX_BD_QUEUES_ALIGNMENT);
|
|
uec->p_rx_bd_qs_tbl = (struct uec_rx_bd_queues_entry *)
|
|
qe_muram_addr(uec->rx_bd_qs_tbl_offset);
|
|
|
|
/* Zero it */
|
|
memset(uec->p_rx_bd_qs_tbl, 0, sizeof(struct uec_rx_bd_queues_entry) +
|
|
sizeof(struct uec_rx_pref_bds));
|
|
out_be32(&uec->p_rx_glbl_pram->rbdqptr, uec->rx_bd_qs_tbl_offset);
|
|
out_be32(&uec->p_rx_bd_qs_tbl->externalbdbaseptr,
|
|
(u32)uec->p_rx_bd_ring);
|
|
|
|
/* MFLR */
|
|
out_be16(&uec->p_rx_glbl_pram->mflr, MAX_FRAME_LEN);
|
|
/* MINFLR */
|
|
out_be16(&uec->p_rx_glbl_pram->minflr, MIN_FRAME_LEN);
|
|
/* MAXD1 */
|
|
out_be16(&uec->p_rx_glbl_pram->maxd1, MAX_DMA1_LEN);
|
|
/* MAXD2 */
|
|
out_be16(&uec->p_rx_glbl_pram->maxd2, MAX_DMA2_LEN);
|
|
/* ECAM_PTR */
|
|
out_be32(&uec->p_rx_glbl_pram->ecamptr, 0);
|
|
/* L2QT */
|
|
out_be32(&uec->p_rx_glbl_pram->l2qt, 0);
|
|
/* L3QT */
|
|
for (i = 0; i < 8; i++)
|
|
out_be32(&uec->p_rx_glbl_pram->l3qt[i], 0);
|
|
|
|
/* VLAN_TYPE */
|
|
out_be16(&uec->p_rx_glbl_pram->vlantype, 0x8100);
|
|
/* TCI */
|
|
out_be16(&uec->p_rx_glbl_pram->vlantci, 0);
|
|
|
|
/* Clear PQ2 style address filtering hash table */
|
|
p_af_pram = (struct uec_82xx_add_filtering_pram *)
|
|
uec->p_rx_glbl_pram->addressfiltering;
|
|
|
|
p_af_pram->iaddr_h = 0;
|
|
p_af_pram->iaddr_l = 0;
|
|
p_af_pram->gaddr_h = 0;
|
|
p_af_pram->gaddr_l = 0;
|
|
}
|
|
|
|
static int uec_issue_init_enet_rxtx_cmd(struct uec_priv *uec,
|
|
int thread_tx, int thread_rx)
|
|
{
|
|
struct uec_init_cmd_pram *p_init_enet_param;
|
|
u32 init_enet_param_offset;
|
|
struct uec_inf *uec_info;
|
|
struct ucc_fast_inf *uf_info;
|
|
int i;
|
|
int snum;
|
|
u32 off;
|
|
u32 entry_val;
|
|
u32 command;
|
|
u32 cecr_subblock;
|
|
|
|
uec_info = uec->uec_info;
|
|
uf_info = &uec_info->uf_info;
|
|
|
|
/* Allocate init enet command parameter */
|
|
uec->init_enet_param_offset =
|
|
qe_muram_alloc(sizeof(struct uec_init_cmd_pram), 4);
|
|
init_enet_param_offset = uec->init_enet_param_offset;
|
|
uec->p_init_enet_param = (struct uec_init_cmd_pram *)
|
|
qe_muram_addr(uec->init_enet_param_offset);
|
|
|
|
/* Zero init enet command struct */
|
|
memset((void *)uec->p_init_enet_param, 0,
|
|
sizeof(struct uec_init_cmd_pram));
|
|
|
|
/* Init the command struct */
|
|
p_init_enet_param = uec->p_init_enet_param;
|
|
p_init_enet_param->resinit0 = ENET_INIT_PARAM_MAGIC_RES_INIT0;
|
|
p_init_enet_param->resinit1 = ENET_INIT_PARAM_MAGIC_RES_INIT1;
|
|
p_init_enet_param->resinit2 = ENET_INIT_PARAM_MAGIC_RES_INIT2;
|
|
p_init_enet_param->resinit3 = ENET_INIT_PARAM_MAGIC_RES_INIT3;
|
|
p_init_enet_param->resinit4 = ENET_INIT_PARAM_MAGIC_RES_INIT4;
|
|
p_init_enet_param->largestexternallookupkeysize = 0;
|
|
|
|
p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_rx)
|
|
<< ENET_INIT_PARAM_RGF_SHIFT;
|
|
p_init_enet_param->rgftgfrxglobal |= ((u32)uec_info->num_threads_tx)
|
|
<< ENET_INIT_PARAM_TGF_SHIFT;
|
|
|
|
/* Init Rx global parameter pointer */
|
|
p_init_enet_param->rgftgfrxglobal |= uec->rx_glbl_pram_offset |
|
|
(u32)uec_info->risc_rx;
|
|
|
|
/* Init Rx threads */
|
|
for (i = 0; i < (thread_rx + 1); i++) {
|
|
snum = qe_get_snum();
|
|
if (snum < 0) {
|
|
printf("%s can not get snum\n", __func__);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
if (i == 0) {
|
|
off = 0;
|
|
} else {
|
|
off = qe_muram_alloc(sizeof(struct uec_thread_rx_pram),
|
|
UEC_THREAD_RX_PRAM_ALIGNMENT);
|
|
}
|
|
|
|
entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
|
|
off | (u32)uec_info->risc_rx;
|
|
p_init_enet_param->rxthread[i] = entry_val;
|
|
}
|
|
|
|
/* Init Tx global parameter pointer */
|
|
p_init_enet_param->txglobal = uec->tx_glbl_pram_offset |
|
|
(u32)uec_info->risc_tx;
|
|
|
|
/* Init Tx threads */
|
|
for (i = 0; i < thread_tx; i++) {
|
|
snum = qe_get_snum();
|
|
if (snum < 0) {
|
|
printf("%s can not get snum\n", __func__);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
off = qe_muram_alloc(sizeof(struct uec_thread_tx_pram),
|
|
UEC_THREAD_TX_PRAM_ALIGNMENT);
|
|
|
|
entry_val = ((u32)snum << ENET_INIT_PARAM_SNUM_SHIFT) |
|
|
off | (u32)uec_info->risc_tx;
|
|
p_init_enet_param->txthread[i] = entry_val;
|
|
}
|
|
|
|
__asm__ __volatile__("sync");
|
|
|
|
/* Issue QE command */
|
|
command = QE_INIT_TX_RX;
|
|
cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num);
|
|
qe_issue_cmd(command, cecr_subblock, (u8)QE_CR_PROTOCOL_ETHERNET,
|
|
init_enet_param_offset);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int uec_startup(struct udevice *dev)
|
|
{
|
|
struct qe_uec_priv *priv = dev_get_priv(dev);
|
|
struct uec_priv *uec = priv->uec;
|
|
struct uec_inf *uec_info;
|
|
struct ucc_fast_inf *uf_info;
|
|
struct ucc_fast_priv *uccf;
|
|
ucc_fast_t *uf_regs;
|
|
uec_t *uec_regs;
|
|
int num_threads_tx;
|
|
int num_threads_rx;
|
|
u32 utbipar;
|
|
u32 length;
|
|
u32 align;
|
|
struct buffer_descriptor *bd;
|
|
u8 *buf;
|
|
int i;
|
|
|
|
uec_info = uec->uec_info;
|
|
uf_info = &uec_info->uf_info;
|
|
|
|
/* Check if Rx BD ring len is illegal */
|
|
if (uec_info->rx_bd_ring_len < UEC_RX_BD_RING_SIZE_MIN ||
|
|
uec_info->rx_bd_ring_len % UEC_RX_BD_RING_SIZE_ALIGNMENT) {
|
|
printf("%s: Rx BD ring len must be multiple of 4, and > 8.\n",
|
|
__func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Check if Tx BD ring len is illegal */
|
|
if (uec_info->tx_bd_ring_len < UEC_TX_BD_RING_SIZE_MIN) {
|
|
printf("%s: Tx BD ring length must not be smaller than 2.\n",
|
|
__func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Check if MRBLR is illegal */
|
|
if (MAX_RXBUF_LEN == 0 || (MAX_RXBUF_LEN % UEC_MRBLR_ALIGNMENT)) {
|
|
printf("%s: max rx buffer length must be mutliple of 128.\n",
|
|
__func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Both Rx and Tx are stopped */
|
|
uec->grace_stopped_rx = 1;
|
|
uec->grace_stopped_tx = 1;
|
|
|
|
/* Init UCC fast */
|
|
if (ucc_fast_init(uf_info, &uccf)) {
|
|
printf("%s: failed to init ucc fast\n", __func__);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* Save uccf */
|
|
uec->uccf = uccf;
|
|
|
|
/* Convert the Tx threads number */
|
|
if (uec_convert_threads_num(uec_info->num_threads_tx,
|
|
&num_threads_tx))
|
|
return -EINVAL;
|
|
|
|
/* Convert the Rx threads number */
|
|
if (uec_convert_threads_num(uec_info->num_threads_rx,
|
|
&num_threads_rx))
|
|
return -EINVAL;
|
|
|
|
uf_regs = uccf->uf_regs;
|
|
|
|
/* UEC register is following UCC fast registers */
|
|
uec_regs = (uec_t *)(&uf_regs->ucc_eth);
|
|
|
|
/* Save the UEC register pointer to UEC private struct */
|
|
uec->uec_regs = uec_regs;
|
|
|
|
/* Init UPSMR, enable hardware statistics (UCC) */
|
|
out_be32(&uec->uccf->uf_regs->upsmr, UPSMR_INIT_VALUE);
|
|
|
|
/* Init MACCFG1, flow control disable, disable Tx and Rx */
|
|
out_be32(&uec_regs->maccfg1, MACCFG1_INIT_VALUE);
|
|
|
|
/* Init MACCFG2, length check, MAC PAD and CRC enable */
|
|
out_be32(&uec_regs->maccfg2, MACCFG2_INIT_VALUE);
|
|
|
|
/* Setup UTBIPAR */
|
|
utbipar = in_be32(&uec_regs->utbipar);
|
|
utbipar &= ~UTBIPAR_PHY_ADDRESS_MASK;
|
|
|
|
/* Initialize UTBIPAR address to CONFIG_UTBIPAR_INIT_TBIPA for ALL UEC.
|
|
* This frees up the remaining SMI addresses for use.
|
|
*/
|
|
utbipar |= CONFIG_UTBIPAR_INIT_TBIPA << UTBIPAR_PHY_ADDRESS_SHIFT;
|
|
out_be32(&uec_regs->utbipar, utbipar);
|
|
|
|
/* Allocate Tx BDs */
|
|
length = ((uec_info->tx_bd_ring_len * SIZEOFBD) /
|
|
UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT) *
|
|
UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
|
|
if ((uec_info->tx_bd_ring_len * SIZEOFBD) %
|
|
UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT)
|
|
length += UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT;
|
|
|
|
align = UEC_TX_BD_RING_ALIGNMENT;
|
|
uec->tx_bd_ring_offset = (u32)malloc((u32)(length + align));
|
|
if (uec->tx_bd_ring_offset != 0)
|
|
uec->p_tx_bd_ring = (u8 *)((uec->tx_bd_ring_offset + align)
|
|
& ~(align - 1));
|
|
|
|
/* Zero all of Tx BDs */
|
|
memset((void *)(uec->tx_bd_ring_offset), 0, length + align);
|
|
|
|
/* Allocate Rx BDs */
|
|
length = uec_info->rx_bd_ring_len * SIZEOFBD;
|
|
align = UEC_RX_BD_RING_ALIGNMENT;
|
|
uec->rx_bd_ring_offset = (u32)(malloc((u32)(length + align)));
|
|
if (uec->rx_bd_ring_offset != 0)
|
|
uec->p_rx_bd_ring = (u8 *)((uec->rx_bd_ring_offset + align)
|
|
& ~(align - 1));
|
|
|
|
/* Zero all of Rx BDs */
|
|
memset((void *)(uec->rx_bd_ring_offset), 0, length + align);
|
|
|
|
/* Allocate Rx buffer */
|
|
length = uec_info->rx_bd_ring_len * MAX_RXBUF_LEN;
|
|
align = UEC_RX_DATA_BUF_ALIGNMENT;
|
|
uec->rx_buf_offset = (u32)malloc(length + align);
|
|
if (uec->rx_buf_offset != 0)
|
|
uec->p_rx_buf = (u8 *)((uec->rx_buf_offset + align)
|
|
& ~(align - 1));
|
|
|
|
/* Zero all of the Rx buffer */
|
|
memset((void *)(uec->rx_buf_offset), 0, length + align);
|
|
|
|
/* Init TxBD ring */
|
|
bd = (struct buffer_descriptor *)uec->p_tx_bd_ring;
|
|
uec->tx_bd = bd;
|
|
|
|
for (i = 0; i < uec_info->tx_bd_ring_len; i++) {
|
|
BD_DATA_CLEAR(bd);
|
|
BD_STATUS_SET(bd, 0);
|
|
BD_LENGTH_SET(bd, 0);
|
|
bd++;
|
|
}
|
|
BD_STATUS_SET((--bd), TX_BD_WRAP);
|
|
|
|
/* Init RxBD ring */
|
|
bd = (struct buffer_descriptor *)uec->p_rx_bd_ring;
|
|
uec->rx_bd = bd;
|
|
buf = uec->p_rx_buf;
|
|
for (i = 0; i < uec_info->rx_bd_ring_len; i++) {
|
|
BD_DATA_SET(bd, buf);
|
|
BD_LENGTH_SET(bd, 0);
|
|
BD_STATUS_SET(bd, RX_BD_EMPTY);
|
|
buf += MAX_RXBUF_LEN;
|
|
bd++;
|
|
}
|
|
BD_STATUS_SET((--bd), RX_BD_WRAP | RX_BD_EMPTY);
|
|
|
|
/* Init global Tx parameter RAM */
|
|
uec_init_tx_parameter(uec, num_threads_tx);
|
|
|
|
/* Init global Rx parameter RAM */
|
|
uec_init_rx_parameter(uec, num_threads_rx);
|
|
|
|
/* Init ethernet Tx and Rx parameter command */
|
|
if (uec_issue_init_enet_rxtx_cmd(uec, num_threads_tx,
|
|
num_threads_rx)) {
|
|
printf("%s issue init enet cmd failed\n", __func__);
|
|
return -ENOMEM;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/* Convert a string to a QE clock source enum
|
|
*
|
|
* This function takes a string, typically from a property in the device
|
|
* tree, and returns the corresponding "enum qe_clock" value.
|
|
*/
|
|
enum qe_clock qe_clock_source(const char *source)
|
|
{
|
|
unsigned int i;
|
|
|
|
if (strcasecmp(source, "none") == 0)
|
|
return QE_CLK_NONE;
|
|
|
|
if (strncasecmp(source, "brg", 3) == 0) {
|
|
i = simple_strtoul(source + 3, NULL, 10);
|
|
if (i >= 1 && i <= 16)
|
|
return (QE_BRG1 - 1) + i;
|
|
else
|
|
return QE_CLK_DUMMY;
|
|
}
|
|
|
|
if (strncasecmp(source, "clk", 3) == 0) {
|
|
i = simple_strtoul(source + 3, NULL, 10);
|
|
if (i >= 1 && i <= 24)
|
|
return (QE_CLK1 - 1) + i;
|
|
else
|
|
return QE_CLK_DUMMY;
|
|
}
|
|
|
|
return QE_CLK_DUMMY;
|
|
}
|
|
|
|
static void qe_uec_set_eth_type(struct udevice *dev)
|
|
{
|
|
struct qe_uec_priv *priv = dev_get_priv(dev);
|
|
struct uec_priv *uec = priv->uec;
|
|
struct uec_inf *uec_info = uec->uec_info;
|
|
struct ucc_fast_inf *uf_info = &uec_info->uf_info;
|
|
|
|
switch (uec_info->enet_interface_type) {
|
|
case PHY_INTERFACE_MODE_GMII:
|
|
case PHY_INTERFACE_MODE_RGMII:
|
|
case PHY_INTERFACE_MODE_RGMII_ID:
|
|
case PHY_INTERFACE_MODE_RGMII_RXID:
|
|
case PHY_INTERFACE_MODE_RGMII_TXID:
|
|
case PHY_INTERFACE_MODE_TBI:
|
|
case PHY_INTERFACE_MODE_RTBI:
|
|
case PHY_INTERFACE_MODE_SGMII:
|
|
uf_info->eth_type = GIGA_ETH;
|
|
break;
|
|
default:
|
|
uf_info->eth_type = FAST_ETH;
|
|
break;
|
|
}
|
|
}
|
|
|
|
static int qe_uec_set_uec_info(struct udevice *dev)
|
|
{
|
|
struct qe_uec_priv *priv = dev_get_priv(dev);
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
struct uec_priv *uec = priv->uec;
|
|
struct uec_inf *uec_info;
|
|
struct ucc_fast_inf *uf_info;
|
|
const char *s;
|
|
int ret;
|
|
u32 val;
|
|
|
|
uec_info = (struct uec_inf *)malloc(sizeof(struct uec_inf));
|
|
if (!uec_info)
|
|
return -ENOMEM;
|
|
|
|
uf_info = &uec_info->uf_info;
|
|
|
|
ret = dev_read_u32(dev, "cell-index", &val);
|
|
if (ret) {
|
|
ret = dev_read_u32(dev, "device-id", &val);
|
|
if (ret) {
|
|
pr_err("no cell-index nor device-id found!");
|
|
goto out;
|
|
}
|
|
}
|
|
|
|
uf_info->ucc_num = val - 1;
|
|
if (uf_info->ucc_num < 0 || uf_info->ucc_num > 7) {
|
|
ret = -ENODEV;
|
|
goto out;
|
|
}
|
|
|
|
ret = dev_read_string_index(dev, "rx-clock-name", 0, &s);
|
|
if (!ret) {
|
|
uf_info->rx_clock = qe_clock_source(s);
|
|
if (uf_info->rx_clock < QE_CLK_NONE ||
|
|
uf_info->rx_clock > QE_CLK24) {
|
|
pr_err("invalid rx-clock-name property\n");
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
} else {
|
|
ret = dev_read_u32(dev, "rx-clock", &val);
|
|
if (ret) {
|
|
/*
|
|
* If both rx-clock-name and rx-clock are missing,
|
|
* we want to tell people to use rx-clock-name.
|
|
*/
|
|
pr_err("missing rx-clock-name property\n");
|
|
goto out;
|
|
}
|
|
if (val < QE_CLK_NONE || val > QE_CLK24) {
|
|
pr_err("invalid rx-clock property\n");
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
uf_info->rx_clock = val;
|
|
}
|
|
|
|
ret = dev_read_string_index(dev, "tx-clock-name", 0, &s);
|
|
if (!ret) {
|
|
uf_info->tx_clock = qe_clock_source(s);
|
|
if (uf_info->tx_clock < QE_CLK_NONE ||
|
|
uf_info->tx_clock > QE_CLK24) {
|
|
pr_err("invalid tx-clock-name property\n");
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
} else {
|
|
ret = dev_read_u32(dev, "tx-clock", &val);
|
|
if (ret) {
|
|
pr_err("missing tx-clock-name property\n");
|
|
goto out;
|
|
}
|
|
if (val < QE_CLK_NONE || val > QE_CLK24) {
|
|
pr_err("invalid tx-clock property\n");
|
|
ret = -EINVAL;
|
|
goto out;
|
|
}
|
|
uf_info->tx_clock = val;
|
|
}
|
|
|
|
uec_info->num_threads_tx = UEC_NUM_OF_THREADS_1;
|
|
uec_info->num_threads_rx = UEC_NUM_OF_THREADS_1;
|
|
uec_info->risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2;
|
|
uec_info->risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2;
|
|
uec_info->tx_bd_ring_len = 16;
|
|
uec_info->rx_bd_ring_len = 16;
|
|
#if (MAX_QE_RISC == 4)
|
|
uec_info->risc_tx = QE_RISC_ALLOCATION_FOUR_RISCS;
|
|
uec_info->risc_rx = QE_RISC_ALLOCATION_FOUR_RISCS;
|
|
#endif
|
|
|
|
uec_info->enet_interface_type = pdata->phy_interface;
|
|
|
|
uec->uec_info = uec_info;
|
|
qe_uec_set_eth_type(dev);
|
|
|
|
return 0;
|
|
out:
|
|
free(uec_info);
|
|
return ret;
|
|
}
|
|
|
|
static int qe_uec_probe(struct udevice *dev)
|
|
{
|
|
struct qe_uec_priv *priv = dev_get_priv(dev);
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
struct uec_priv *uec;
|
|
int ret;
|
|
|
|
/* Allocate the UEC private struct */
|
|
uec = (struct uec_priv *)malloc(sizeof(struct uec_priv));
|
|
if (!uec)
|
|
return -ENOMEM;
|
|
|
|
memset(uec, 0, sizeof(struct uec_priv));
|
|
priv->uec = uec;
|
|
uec->uec_regs = (uec_t *)pdata->iobase;
|
|
|
|
/* setup uec info struct */
|
|
ret = qe_uec_set_uec_info(dev);
|
|
if (ret) {
|
|
free(uec);
|
|
return ret;
|
|
}
|
|
|
|
ret = uec_startup(dev);
|
|
if (ret) {
|
|
free(uec->uec_info);
|
|
free(uec);
|
|
return ret;
|
|
}
|
|
|
|
priv->phydev = dm_eth_phy_connect(dev);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Remove the driver from an interface:
|
|
* - free up allocated memory
|
|
*/
|
|
static int qe_uec_remove(struct udevice *dev)
|
|
{
|
|
struct qe_uec_priv *priv = dev_get_priv(dev);
|
|
|
|
free(priv->uec);
|
|
return 0;
|
|
}
|
|
|
|
static int qe_uec_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
const char *phy_mode;
|
|
|
|
pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
|
|
|
|
pdata->phy_interface = -1;
|
|
phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
|
|
"phy-connection-type", NULL);
|
|
if (phy_mode)
|
|
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
|
|
if (pdata->phy_interface == -1) {
|
|
debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id qe_uec_ids[] = {
|
|
{ .compatible = QE_UEC_DRIVER_NAME },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(eth_qe_uec) = {
|
|
.name = QE_UEC_DRIVER_NAME,
|
|
.id = UCLASS_ETH,
|
|
.of_match = qe_uec_ids,
|
|
.ofdata_to_platdata = qe_uec_ofdata_to_platdata,
|
|
.probe = qe_uec_probe,
|
|
.remove = qe_uec_remove,
|
|
.ops = &qe_uec_eth_ops,
|
|
.priv_auto_alloc_size = sizeof(struct qe_uec_priv),
|
|
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
|
|
};
|